mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 70

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
4.8.4
DRAM Data input timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2.
4.9
The following sections provide information on external peripheral interfaces.
4.9.1
The AUDMUX provides programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module.
70
DDR20
DDR21
DDR22
ID
External Peripheral Interfaces
DRAM Data Input Timing
AUDMUX Timing Parameters
Positive DQS latching edge to associated CK edge
DQS to DQ input skew
DQS to DQ input hold time
DRAM_SDCLK_B
DRAM_SDCLK
DRAM_SDQS_B
DRAM_SDQS
DRAM_D
The timing parameter DDR20(tDQSCK) is not strictly required by this
DRAM MC design.
i.MX50 Applications Processors for Consumer Products, Rev. 0
Description
Figure 31. DRAM Data Input Timing
Table 45. DDR2 Input AC Timing
DDR20
DDR21
NOTE
d0
tDQSCK
Symbol
tDQSQ
DDR22
d1
tQH
d2
0.45 tCK
-0.5 tCK
-0.85
d3
Min
—
Freescale Semiconductor
Max
0.65
—
—
Unit
ns
ns
ns