mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 68

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
4.8.3
The DRAM data output timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2.
68
CK >= 200 MHz
CK >= 200 MHz
CK < 200 MHz
CK < 200 MHz
DDR5
DDR6
DDR7
DDR6
DDR7
ID
DRAM Data Output Timing
DRAM_SDCLK_B
DRAM_SDCLK
DRAM_SDQS_B
DRAM_SDQS
DRAM_D &
DRAM_DQM
DDR6 and DDR7 can be adjusted by the parameter -DLL_WR_DELAY-;
The ideal case is that SDCLK is center aligned to the DRAM_A[9:0] data
valid window;
For this table, HW_DRAM_PHY23[14:8] (DLL_WR_DELAY) = 0x10;
Control output hold time
Address output setup time
Address output hold time
Address output setup time
Address output hold time
i.MX50 Applications Processors for Consumer Products, Rev. 0
Table 43. EMI Command/Address AC Timing (continued)
Description
Figure 30. DRAM Data Output Timing
DDR10
DDR13
NOTE
Symbol
d0
tIH
tIS
tIH
tIS
tIH
d1
DDR11
DDR15
DDR16
0.5 tCK
0.5 tCK
0.5 tCK
d2
- 0.3
- 1.3
- 1.3
Min
1
1
DDR14
d3
DDR12
Max
—
—
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns