mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 88

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mcimx50

Manufacturer Part Number
mcimx50
Description
I.mx50 Applications Processors For Consumer Products
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Electrical Characteristics
88
SS17
SS18
SS19
SS42
SS43
SS52
ID
STXD rise/fall time
SRXD setup before (Tx) CK falling
(Tx) CK high to STXD high/low
(Tx) CK high to STXD high impedance
SRXD hold after (Tx) CK falling
Loading
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in both the
tables and figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
The terms WL and BL refer to word length (WL) and bit length (BL).
Tx and Rx refer to the transmit and receive sections of the SSI.
For internal frame sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
Table 63. SSI Transmitter Timing with Internal Clock (continued)
i.MX50 Applications Processors for Consumer Products, Rev. 0
Parameter
Synchronous Internal Clock Operation
NOTE
10.0
Min
0.0
Freescale Semiconductor
Max
15.0
15.0
25.0
6.0
Unit
pF
ns
ns
ns
ns
ns

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