tc59lm913amb-50 TOSHIBA Semiconductor CORPORATION, tc59lm913amb-50 Datasheet
tc59lm913amb-50
Related parts for tc59lm913amb-50
tc59lm913amb-50 Summary of contents
Page 1
... Package: 60Ball BGA, 1mm × 1mm Ball pitch (P−BGA64−1317−1.00AZ) Notice : FCRAM is trademark of Fujitsu Limited, Japan. TC59LM913AMB-50 5.0 ns 25.0 ns 22.0 ns 240 4,194,304 words × 8 banks × 16 bits 2.5 V ± 0.15V 2.5 V ± 0.15 V TC59LM913AMB- capable of high quality fast data Rev 1.1 2005-11-08 1/46 ...
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... V DD DQ8 UDQS LDQS V VREF V SS CLK CLK A12 PD A11 A9 BA1 TC59LM913AMB-50 NAME Power (+2.5 V) Ground Power (+2.5 V) (for I/O buffer) Ground (for I/O buffer) Reference Voltage Not Connected DQ1 DD DQ2 Q SS DQ3 Q DQ5 DD Q DQ6 NC SS DQ7 Q ...
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... Note: TC59LM913AMB configuration is 8 Bank of 16384 x 256 cell array with DQ pins numbered DQ0~DQ15. To each block CONTROL SIGNAL MODE REGISTER UPPER ADDRESS LATCH LOWER ADDRESS LATCH WRITE ADDRESS LATCH/ ADDRESS COMPARATOR BURST COUNTER TC59LM913AMB-50 BANK #7 BANK #6 BANK #5 BANK #4 BANK #3 BANK #2 BANK #1 BANK #0 MEMORY CELL ARRAY COLUMN DECODER READ DATA BUFFER DQ BUFFER ...
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... Differential Clock AC Middle Level ISO PARAMETER −0.3~V −0.3~V −0.3~V −0.3~V MIN 2.35 2.35 /2 × 96% V DDQ + 0.2 V REF −0.1 −0.1 0.4 + 0.35 V REF −0.1 0.7 /2 − 0.2 V DDQ /2 − 0.2 V DDQ TC59LM913AMB-50 RATING UNIT −0.3 0.3 V DDQ + 0 0~85 °C −55~150 °C 260 ° ± 0~85°C) (Notes: 1)(T CASE TYP ...
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... V with a pulse width ≤ 5 ns. DDQ = −0.9 V with a pulse width ≤ the transmitting device. DDQ ( CLK )} /2 ICK ICK V (min) ISO ISO = 2 MHz 25°C) DDQ PARAMETER TC59LM913AMB-50 (DC ICK ICK (max) MIN MAX Delta 1.5 2.5 0.25 1.5 2 ...
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... IH IN DDQ = 0mA ; OUT (AC) (min) ≤ V ≤ DDQ interval ; REFC (AC) (min) ≤ V ≤ DDQ . REFC ≤ DDQ and TC59LM913AMB-50 MAX UNIT NOTES 240 1, 2 100 350 350 1, 2 250 REFI Rev 1.1 2005-11-08 6/46 ...
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... Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register. = 0~85°C) CASE PARAMETER ≤ OUT DDQ = V − 0.4V DDQ = 0. − 0.4V DDQ = 0. − 0.4V DDQ = 0. − 0.4V DDQ = 0.4V TC59LM913AMB-50 MIN MAX UNIT NOTES −5 µA 5 −5 µA 5 −5 µA 5 −10 10 −11 − ...
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... Data Input Setup Time from L/UDQS DS t Data Input Hold Time from L/UDQS DH t Command/Address Input Setup Time IS t Command/Address Input Hold Time IH = 2.5V ± 0.15V 0~85°C) CASE 0.9 × min TC59LM913AMB-50 (Notes MIN MAX UNIT 25 5.0 8.5 22.0 0.45 × t CK 0.45 × t CK −0.65 0.65 ...
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... PDA I Power down mode valid from REF command PDV I Auto-Refresh Cycle Time REFC I REF Command to Clock Input Disable at Self-Refresh Entry CKD I DLL Lock-on Time (applicable to RDA command) LOCK TC59LM913AMB-50 (Notes (continued) MIN −0.65 −0.65 −0.65 0 0.9 0.1 −0.5 × 0.4 200 ...
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... V REF V (AC) IL max ∆T (AC))/∆T (DC) and V IH min IL max contains more than one decimal place, the result ns, 0.75 × 3. rounded up to 3.8 ns.) /2 ± 0.2 V from steady state. DDQ TC59LM913AMB-50 VALUE UNIT NOTES + 0. REF − 0. REF DDQ ...
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... DDQ . REF 2.5V(TYP) 2.5V(TYP) 1.25V(TYP RSC RSC l PDA RDA MRS DESL RDA MRS DESL WRA REF DESL op-code op-code EMRS MRS EMRS MRS TC59LM913AMB- REFC REFC 200clock cycle(min) DESL WRA REF DESL Auto Refresh cycle Normal Operation Rev 1.1 2005-11-08 11/46 ...
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... 1st 2nd UA TC59LM913AMB- Refer to the Command Truth Table (AC (AC Rev 1.1 2005-11-08 12/46 (AC) ...
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... Note: DQ0 to DQ15 are aligned with LDQS/UDQS. The correspondence of LDQS, UDQS to DQ are as follows. CK DESL t t QSLZ t CKQS t QSPRE Preamble QSQ LDQS DQ0∼DQ7 UDQS DQ8∼DQ15 TC59LM913AMB-50 CKQS t CKQS QSP QSP QSHZ Postamble t t QSQV QSQ QSQ QSQV HZ Q1 ...
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... Note: DQ0 to DQ15 are aligned with LDQS/UDQS. The correspondence of LDQS, UDQS to DQ are as follows. DESL t DSS t t DSPSTH DSS t DSPRES DSP DSP DSP DSPST t DSPREH Preamble Postamble t DSPRE DQSS DQSS LDQS DQ0∼DQ7 UDQS DQ8∼DQ15 TC59LM913AMB-50 Rev 1.1 2005-11-08 14/46 ...
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... Ixxxx Timing REFI PAUSE CLK CLK Input (control & addresses) Command Note: “I ” means “I XXXX REFI PAUSE XXXX ”, “I ”, “I ”, etc. RC RCD RAS TC59LM913AMB- Command Rev 1.1 2005-11-08 15/46 ...
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... Write Timing (x16 device) (Burst Length =4) CLK CLK Input WRA LAL (control & addresses) CAS latency = 4 LDQS DQ0~DQ7 UDQS DQ8~DQ15 TC59LM913AMB-50 DESL DSSK DSSK DSSK DSSK Preamble Preamble ...
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... L × BA1~BA0 BA2 × × × BA1~BA0 BA2 A13 × × H LVW0 LVW1 TC59LM913AMB-50 A13~A9 A8 A7~A0 × × × A10~A9 A8 A7~A0 × × × × × × A13~A9 A8 A7~ × ...
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... Self-Refresh L L Self-Refresh CURRENT CS STATE n − Standby × Power Down L L Power Down from REF command. FPDL TC59LM913AMB-50 FN BA2~BA0 A13~A8 A7~A0 × × × H × BA2~BA0 A13~A8 A7~A0 × × × L × × × × FN BA2~BA0 ...
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... H SELFX × × L TC59LM913AMB-50 ACTION NOTES NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State Begin Read Illegal Invalid Begin Write Auto-Refresh Illegal ...
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... BA0 BA2, A13~ DIC A6 A1 OUTPUT DRIVE IMPEDANCE CONTROL (DIC Normal Output Driver 0 1 Strong Output Driver 1 0 Weaker Output Driver 1 1 Weakest Output Driver TC59LM913AMB-50 A6~A4 A3 A2~ BURST TYPE (BT) 0 Sequential 1 Interleave A1 A0 BURST LENGTH (BL Reserved 0 ...
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... STANDBY (IDLE) WRA RDA ACTIVE ACTIVE (RESTORE) LAL WRITE READ (BUFFER) TC59LM913AMB-50 POWER DOWN PDEN ( MODE REGISTER MRS LAL Command input Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input. 2005-11-08 21/46 ...
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... I RC RDA LAL DESL = cycles I I RAS RCD TC59LM913AMB- cycles I RC RDA LAL DESL =1 cycle = 4 cycles I I RCD RAS 2005-11-08 22/46 ...
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... DQ (input L/UDQS (input (input cycles I RC WRA LAL DESL TC59LM913AMB- cycles I RC WRA LAL DESL 2005-11-08 23/46 15 WRA UA #0 Rev 1.1 ...
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... Hi-Z L/UDQS Hi Hi-Z L/UDQS Hi cycles I RC WRA LAL DESL TC59LM913AMB- cycles I RC RDA LAL DESL 2005-11-08 24/46 15 WRA Rev 1.1 ...
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... I I RBD RBD DESL RDA LAL RDA LAL Bank Bank "a" "b" (Bank"b" cycles Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 TC59LM913AMB- cycles = 2 cycles I RBD RBD RDA LAL RDA LAL RDA LAL ...
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... WRA LAL WRA LAL WRA Bank Bank Bank "a" "b" (Bank"b" cycles Da0 Da1 Db0Db1 Da0 Da1 Da2Da3Db0Db1Db2Db3 TC59LM913AMB- cycles cycles RBD RBD LAL WRA LAL WRA LAL ...
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... I I RWD WRD RWD Bank Bank "c" "d" I (Bank"a" (Bank"b" Da0 Da1 Qb0 Qb1 TC59LM913AMB- DESL WRA LAL RDA LAL DESL = 2 cycles Bank Bank "a" "b" ...
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... I I RWD WRD Bank Bank "c" "d" I (Bank"a" (Bank"b" Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 TC59LM913AMB- DESL LAL WRA LAL RDA = 3 cycles = 1 cycle I I RWD WRD Bank Bank " ...
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... Bank "a" WRA LAL DESL LA=#1 UA VW=1 VW0 = High VW1 = High Bank "a" Last three data are masked. TC59LM913AMB- DESL D0 #1 (#0) Last one data is masked. WRA LAL DESL LA=#2 UA VW=2 VW0 = Low VW1 = High Bank " ...
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... When PD is brought to "High", a valid executable command may be applied DESL = 1 cycle QPDH l RC(min Power Down Entry (max.) to maintain the data written into cell. REFI TC59LM913AMB-50 10 n-2 n-1 n n+1 n+2 I PDA RDA DESL or WRA UA t PDEX , t REFI(max) Hi-Z Power Down Exit cycles later. PDA Rev 1.1 2005-11-08 30/46 ...
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... When PD is brought to "High", a valid executable command may be applied DESL = 1 cycle clock cycles l RC(min (max.) to maintain the data written into cell. REFI TC59LM913AMB-50 10 n-2 n-1 n n+1 n+2 I PDA RDA DESL or WRA UA t PDEX , t REFI(max) cycles later. PDA Rev 1.1 ...
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... DQ (output) Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/ DESL RDA MRS Valid (opcode) BA0="0" BA1="0" BA2="0" TC59LM913AMB- RSC RDA DESL or WRA UA BA 2005-11-08 32/46 15 LAL LA Rev 1 ...
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... DQ (input) Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/ DESL RDA MRS Valid (opcode) BA0="0" BA1="0" BA2="0" TC59LM913AMB- RSC RDA DESL or WRA UA BA 2005-11-08 33/46 15 LAL LA Rev 1 ...
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... DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence DESL RDA MRS Valid (opcode) BA0="1" BA1="0" BA2="0" TC59LM913AMB- RSC RDA DESL or WRA UA BA 2005-11-08 34/46 ...
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... DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/ DESL RDA MRS Valid (opcode) BA0="1" BA1="0" BA2="0" TC59LM913AMB- RSC RDA DESL or WRA UA BA 2005-11-08 35/46 ...
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... I I RAS RCD must be meet 18 clock cycles. REFC must be satisfied WRA REF 8 Refresh cycle TC59LM913AMB-50 n − cycles I REFC RDA DESL or MRS or WRA Hi-Z Hi WRA REF WRA REF + ...
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... I REFC *4 *4 WRA REF DESL = 1 cycle I RCD I LOCK after PD is brought to “High”. REFC . LOCK TC59LM913AMB- (min) and t (max) to Self FPDL (max) and l , TC59LM913AMB PDV − Command (1st) *5 Command (2nd RDA LAL ...
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... LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. 8 bank operation 4 bank operation CS & FN BA0 BA1 UPPER ADDRESS LOWER ADDRESS A0~A13 A0~A7 A0~A13, BA2(A14) A0~A7 TC59LM913AMB- competent Each BA2 Rev 1.1 2005-11-08 38/46 ...
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... V DD DDQ V and V are power supply pins for memory core and peripheral circuits and V are power supply pins for the output buffer. DDQ SSQ REFERENCE VOLTAGE: V REF V is reference voltage for all input signals. REF , SSQ TC59LM913AMB-50 Rev 1.1 2005-11-08 39/46 ...
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... Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for two clocks cycle after PD goes high. The Power Down exit function is asynchronous operation Write Burst Length is controlled by VW0 and RC period. The device is in Self-Refresh mode as long as PD held CKD TC59LM913AMB-50 . However, about a REFC = “L”) PD from the FPDL period. In addition, ...
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... Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst length of 2 and 4 words. BA0 Mode Register Set 0 Regular MRS 1 Extended MRS × Reserved A1 A0 BURST LENGTH 0 0 Reserved words words 1 1 Reserved × × Reserved A3 BURST TYPE 0 Sequential 1 Interleave TC59LM913AMB-50 Rev 1.1 2005-11-08 41/46 ...
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... LA1~LA2 ACCESS ADDRESS CAS LATENCY 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Reserved 1 0 Reserved 1 1 Reserved TC59LM913AMB-50 Data Data Data Data BURST LENGTH 2 words 4 words Rev 1.1 2005-11-08 42/46 ...
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... Reserved field ( A13, BA2) These bits are reserved for future operations and must be set to “0” for normal operation. A1 OUTPUT DRIVER IMPEDANCE CONTROL 0 Normal Output Driver 1 Strong Output Driver 0 Weaker Output Driver 1 Weakest Output Driver TC59LM913AMB-50 Rev 1.1 2005-11-08 43/46 ...
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... PACKAGE DIMENSIONS P-BGA64-1317-1.00AZ Note: In order to support a package, four outer balls located on F and K row are required to assembly to board. These four ball is not connected to any electrical level. Weight: 0.23g (typ.) 16.5 0 13.086 -0.15 0.2 S 0.5 0.05 0. 1.25 B 1.0 2.0 TC59LM913AMB-50 Rev 1.1 2005-11-08 44/46 ...
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... Deleted below sentence because of CL3 feature is dropped( page 1 ). “ Keep backward compatibility for TC59LM814CFT(256Mbits) except package design” dropped. “ • Corrected figure of l based AC timing spec table ( page 11, 30, 31 PDA ) changed from 7.8µs to 3.9µs (page 1, 10, 46). REFI TC59LM913AMB-50 Rev 1.1 2005-11-08 45/46 ...
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... The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. TC59LM913AMB-50 030619EBA Rev 1.1 2005-11-08 46/46 ...