tc59lm913amb-50 TOSHIBA Semiconductor CORPORATION, tc59lm913amb-50 Datasheet - Page 35

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tc59lm913amb-50

Manufacturer Part Number
tc59lm913amb-50
Description
512mbits Network Fcram1 Sstl_2 Interface
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
Command
BA0~BA2
L/UDQS
A13~A0
(input)
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
(input)
From Write operation to Extended Mode Register Set operation.
CLK
CLK
DQ
Note:
WRA
UA
BA
0
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
LAL
LA
1
2
WL+BL/2
3
DESL
D0 D1 D2 D3
4
5
RDA
6
(opcode)
BA0="1"
BA1="0"
BA2="0"
MRS
Valid
7
8
9
10
DESL
I
RSC
11
TC59LM913AMB-50
12
2005-11-08 35/46
13
WRA
RDA
UA
BA
14
or
Rev 1.1
LAL
LA
15

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