tc59lm913amb-50 TOSHIBA Semiconductor CORPORATION, tc59lm913amb-50 Datasheet - Page 30

• Manufacturer Part Number: tc59lm913amb-50
• Description: 512mbits Network Fcram1 Sstl_2 Interface
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Command
Address
L/UDQS
(output)
(output)
POWER DOWN TIMING (CL = 4, BL = 4)
CLK
PD
CLK
Read cycle to Power Down Mode
DQ
Note: PD must be kept "High" level until end of Burst data output.
RDA
UA
0
Hi-Z
Hi-Z
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
PD should be brought to "High" within t
LAL
LA
1
2
CL = 4
3
4
5
Q0 Q1
DESL
REFI
t
6
QPDH
Q2 Q3
(max.) to maintain the data written into cell.
t
IH
Power Down Entry
7
t
IS
8
I
PD
= 1 cycle
9
l
RC(min)
10
, t
REFI(max)
PDA
n-2
TC59LM913AMB-50
cycles later.
n-1
2005-11-08 30/46
Power Down Exit
n
Hi-Z
DESL
n+1
I
PDA
t
PDEX
Rev 1.1
WRA
n+2
RDA
UA
or