tc59lm913amb-50 TOSHIBA Semiconductor CORPORATION, tc59lm913amb-50 Datasheet - Page 31

• Manufacturer Part Number: tc59lm913amb-50
• Description: 512mbits Network Fcram1 Sstl_2 Interface
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Command
L/UDQS
Address
(input)
(input)
POWER DOWN TIMING (CL = 4, BL = 4)
CLK
PD
CLK
Write cycle to Power Down Mode
DQ
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
WRA
UA
0
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
PD should be brought to "High" within t
LAL
LA
1
WL = 3
2
WL = 3
3
D0 D1 D2 D3
4
2 clock cycles
5
DESL
t
REFI
IH
6
(max.) to maintain the data written into cell.
t
IS
7
I
PD
= 1 cycle
8
l
RC(min)
9
10
, t
REFI(max)
PDA
n-2
TC59LM913AMB-50
cycles later.
n-1
2005-11-08 31/46
n
DESL
n+1
I
PDA
t
PDEX
Rev 1.1
WRA
n+2
RDA
UA
or