78q8430-100igt Maxim Integrated Products, Inc., 78q8430-100igt Datasheet - Page 22

• Manufacturer Part Number: 78q8430-100igt
• Description: 10/100 Ethernet Mac And Phy
• Manufacturer: Maxim Integrated Products, Inc.

78Q8430 Data Sheet
5 Host Interface Timing Specification
5.1
Note: On read cycles when MEMWAIT is asserted the DATA outputs will be valid before the
de-assertion of MEMWAIT.
22
Name
T
T
T
T
T
T
T
T
WT
SU
SL
HWT
HCS
HO
L
H
Host Interface
Description
CS and ADDR setup time
Output settling time
Maximum wait time
Wait hold time
CS hold time
ADDR and DATA hold time
WR/OE min low pulse
WR/OE min high pulse
MEMWAIT
WR/OE
ADDR
DATA
CS
Figure 8: Host Interface Timing Diagram
T
SU
T
Requirement
CS and ADDR must be stable on or
before the falling edge of WR/OE.
The maximum amount of time that it will
take the MEMWAIT, or DATA when there
is no MEMWAIT, outputs to become
stable after the falling edge of WR/OE.
The maximum amount of time that the
MEMWAIT output will held asserted.
The minimum amount of time that the
WR/OE input must be held past the
de-assertion of MEMWAIT.
The CS input must be stable low for the
entire duration of the WR/OE low cycle.
The ADDR and DATA inputs must be
stable for no less than this amount of time
after the falling edge of WR.
The minimum amount of time that the
WR/OE inputs must be held low.
The minimum amount of time that the
WR/OE inputs must be held high.
SL
T
T
WT
L
T
HO
T
HWT
T
T
HOWT
HCS
T
H
2.5 ck
10 ns
0 ns
0 ns
2 ck
2 ck
Min
–
–
DS_8430_001
13.7 ns
17 ck
Rev. 1.2
Max
–
–
–
–
–
–