78q8430-100igt Maxim Integrated Products, Inc., 78q8430-100igt Datasheet - Page 58
78q8430-100igt
Manufacturer Part Number
78q8430-100igt
Description
10/100 Ethernet Mac And Phy
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.78Q8430-100IGT.pdf
(88 pages)
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78Q8430 Data Sheet
7.5.6
Note: The default values will vary for static QUEs 2 and 5.
7.5.7
Note: Only bits 31 and 30 are valid for static QUEs 2 and 5.
58
Name: QFLR
Bits
31:23
22:16
15:7
6:0
Name: QSR
Bits
31
30
29:26
25:24
23:19
18
17
16
15
14:8
7
6:0
QUE First/Last Register
QUE Status Register
Type
Type
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
X
X
X
X
X
X
Default
Default
0x00
0x00
0x00
0x00
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
00
0
0
0
0
0
Description
QDR
QUE data is ready.
Pause Mask
When set, pause mode has no effect on the QDR bit for this QUE. The
default behavior when clear is to disallow the setting of the QDR bit in
pause mode.
Reserved
Mode
The current QSR value for the QDR mode.
00 = QDR set when First is not 0
01 = QDR set when above is set.
10 = QDR set when LEOP is not zero.
11 = QDR set when above is set or LEOP is not 0.
Reserved
EOP
The QUE contains at least one EOP.
Above
The Count value is above the threshold.
Below
The Count value is below the threshold.
Reserved
Threshold
The number to compare to Count to determine the above and below
bits.
Reserved
Count
The total number of BLOCKs assigned to this QUE.
Description
Reserved
Last
The value of the Last pointer for this QUE.
Reserved
First
The value of the First pointer for this QUE.
Block: QUE
Block: QUE
Address: 0x01C
Address: 0x018
DS_8430_001
Rev. 1.2
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