78q8430-100igt Maxim Integrated Products, Inc., 78q8430-100igt Datasheet - Page 57

• Manufacturer Part Number: 78q8430-100igt
• Description: 10/100 Ethernet Mac And Phy
• Manufacturer: Maxim Integrated Products, Inc.

DS_8430_001
7.5.3
Note: The PCWR and PSZR must be set before writing to the STDR.
7.5.4
7.5.5
Rev. 1.2
Name: STDR
Bits
31:25
24
23:20
19:18
17:16
15:14
13:0
Name: TDR
Bits
31:0
Name: RDR
Bits
1:0
Setup Transmit Data Register
Transmit Data Register
Receive Data Register
Type
Type
Type
WO
RW
RW
RW
RW
RO
X
X
X
Default
Default
Default
0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
N/A
N/A
00
00
Reset Val: 0x0000_0000
Description
Reserved
Endian
The network transmit byte order.
Set = big endian (Most significant byte transmit first)
Clear = little endian (Least significant byte transmit first)
Reserved
Start Offset
The number of bytes to ignore on the first data word written for this
buffer. This byte mask is applied any time the Count value is
non-zero. After each time it is applied, however, it is reset to zero such
that it is really only applied on the first write.
End Offset
The number of bytes to ignore on the last data word written for this
buffer. This byte mask is applied any time the Count value is zero.
Unlike the Start Offset, the End Offset is not self clearing. This means
that the End Offset will be applied to all writes to the QUE once the
Count value reaches zero, unless the host clears the End Offset. The
remainder of PSZR will override the End Offset when a write occurs
and the PSZR value is less than four.
Reserved
Count
The total number of writes needed to complete the buffer minus one.
This counter decrements on each write operation to the QUE. This
counter decrements on each write operation to the QUE until it reaches
zero. The Count value will remain zero until the next host write. The
value written here must be one less than the number of writes in the
buffer so that the Count value will equal zero on the last write and
cause the End Offset to be applied.
Description
Packet Data Read from the QUE
Data read from this register is shifted out of the QUE to which the
register belongs. The RPSR should be consulted to make sure data is
available before reading this register.
Description
Packet Data to Add to the QUE
Data written to this register is added to the QUE to which the register
belongs.
Block: QUE
Block: QUE
Block: QUE
Address: 0x008
Address: 0x010
Address: 0x00C
78Q8430 Data Sheet
57