78q8430-100igt Maxim Integrated Products, Inc., 78q8430-100igt Datasheet - Page 68

• Manufacturer Part Number: 78q8430-100igt
• Description: 10/100 Ethernet Mac And Phy
• Manufacturer: Maxim Integrated Products, Inc.

78Q8430 Data Sheet
7.6.29 Power Management Control and Status Register
7.6.30 CAM Address Register
68
Name: PMCAP
Bits
15:8
7:0
Name: PMCSR
Bits
31:24
23:22
21:20
19:18
17:16
15
14:9
8
7:2
1:0
Name: CAR
Bits
31:7
6:0
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RO
RO
X
X
X
X
X
Default
Default
Default
0x48
0x01
0x00
Reset Val: 0x120A_4801
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
00
00
00
00
0
0
Description
Next
Reads back 0x48. Points to next capability.
ID
Reads back 0x01.
Description
Reserved
Psmarg1
Voltage regulator #1 margin.
Psmarg2
Voltage regulator #2 margin.
Psmarg3
Voltage regulator #3 margin.
Reserved
PME
Power management event status. This bit is set by a WAKE signal from
the CAM and only cleared when the host writes a 1 to this bit.
Reserved
PME_ENB
Enables assertion of PME when there is a power management event.
Reserved
PS
Present power management state, 01b = D1, 00b = D0. (Any non-zero
value here tells the part that the host is in power down mode). In any
state other than D0, wake signals from classification are allowed to
generate PME interrupts and the movement of receive data into QUEs
is inhibited.
Description
Reserved
ADDR
CAM address of rule being accessed by the RMR and RCR.
Block: CTL
Block: CTL
Block: CTL
Address: 0x198
Address: 0x19C
Address: 0x1A0
DS_8430_001
Rev. 1.2