78q8430-100igt Maxim Integrated Products, Inc., 78q8430-100igt Datasheet - Page 70

• Manufacturer Part Number: 78q8430-100igt
• Description: 10/100 Ethernet Mac And Phy
• Manufacturer: Maxim Integrated Products, Inc.

78Q8430 Data Sheet
7.6.33 Que Status Interrupt Register
Note: All bits are cleared on read.
7.6.34 Que Status Mask Register
70
Name: RCR
Bits
1:0
Name: QSIR
Bits
31
30
29
28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Name: QSMR
Bits
31:0
Type
Type
Type
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Default
Reset Val: 0x0000_0002
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
10
Description
Match Control
How to generate a CAM reference word for the next pass. Match control
is described in detail in
00 = DONE
10 = MD
01 = MX
11 = DROP
Description
QDR Rise
Rising edge detected on QUE 7 QDR bit.
QDR Fall
Falling edge detected on QUE 7 QDR bit.
A Rise
Rising edge detected on QUE 7 QSR A bit. (See QSR)
B Rise
Rising edge detected on QUE 7 QSR B bit. (See QSR)
QUE 6
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 6.
QUE 5
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 5.
QUE 4
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 4.
QUE 3
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 3.
QUE 2
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 2.
QUE 1
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 1.
QUE 0
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 0.
Description
QUE Status Interrupt Mask
When a bit is set it enables the QUE status interrupt for the
corresponding bit in the QSIR. When a bit is clear, the corresponding
bit in the QSIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
Table 27.
Block: CTL
Block: CTL
Block: CTL
Address: 0x1A8
Address: 0x1C0
Address: 0x1C4
DS_8430_001
Rev. 1.2