78q8430-100igt Maxim Integrated Products, Inc., 78q8430-100igt Datasheet - Page 66

• Manufacturer Part Number: 78q8430-100igt
• Description: 10/100 Ethernet Mac And Phy
• Manufacturer: Maxim Integrated Products, Inc.

78Q8430 Data Sheet
7.6.21 Counter Management Register
7.6.22 Snoop Control Register
7.6.23 Interrupt Delay Count Register
7.6.24 Pause Delay Count Register
66
Name: CMR
Bits
31:3
2
1
0
Name: SNCR
Bits
31:7
6:0
Name: IDCR
Bits
31:24
23:0
Name: PDCR
Bits
31:17
16
15:0
Type
Type
Type
Type
RW
RW
RW
WO
RW
W
W
X
X
X
X
Default
Default
Default
Default
0x00
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Description
Reserved
Freeze
When this bit is set, the values of the counters are frozen until the bit is
cleared. Countable events that occur while this bit is set are stored in a
FIFO and processed after the bit is cleared such that no counts are lost.
If the FIFO fills before the Freeze bit is cleared then the bit is
automatically cleared and the counters updated.
Clear Receive
When a 1 is written to this bit then all receive counters are automatically
cleared.
Clear Transmit
When a 1 is written to this bit than all transmit counters are
automatically cleared.
Description
Reserved
BLOCK
Pointer to the BLOCK that is accessed directly via the SNOOP register
space.
Description
Reserved
IDC
How long to delay the data received interrupt, measured in byte times.
Description
Reserved
Start
Start local pause. Writing a one to this bit triggers a local pause
condition immediately.
Pause
How long to halt transmit QUEs for a local pause condition, measured in
delay quanta of 512 Rx bit times.
Block: CTL
Block: CTL
Block: CTL
Block: CTL
Address: 0x16C
Address: 0x170
Address: 0x180
Address: 0x184
DS_8430_001
Rev. 1.2