xr16m890 Exar Corporation, xr16m890 Datasheet - Page 23

• Manufacturer Part Number: xr16m890
• Description: Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

REV. P1.1.1
By default, the RTS# pin is asserted immediately before there is data on the TX output pin. For faster baud
rates, it may be possible that data is lost due to a long start-up time for an RS-485 transceiver. The M890 can
delay the data from 0-15 bit times to allow the RS-485 transceiver to start up
485 Setup Delay” on page
At the end of sending data, the RTS# pin is de-asserted immediately after the TX pin goes idle. The RTS# pin
can be programmed to delay the RTS# from being asserted from 0-15 bit times
485 Turn-Around Delay / Auto RTS Hysteresis” on page
last transmission to reach the farthest station on a long cable network before switching off the line driver.
Normal multidrop mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR[5] = 0 (Special Character
Detect disabled). The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received
(parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to do anything. If the address does not match its slave address, then the receiver
should be disabled.
Auto address detection mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR bit-5 = 1. The
desired slave address will need to be written into the XOFF2 register. The receiver will try to detect an address
byte that matches the porgrammed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the receiver will discard
these data.
automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with
the parity bit (in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will
then receive the subsequent data. If another address byte is received and this address does not match the
programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is
ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity
bit in the parity error bit.
This feature simplifies sending an address byte (9th bit = 1) and improves the efficiency of the transmit data
routine for transmitting 9-bit data. In previous generation UARTs, the only way to send an address byte is by
changing the parity to Forced 1 parity, load the address byte in the THR, wait for the byte to be transmitted,
change the parity back to Forced 0 parity, then load data into the TX FIFO. In the XR16M890, there’s no
waiting required and no changing parity. The transmit routine can set SFR[7]=1, then write the address byte
into the TX FIFO followed immediately by the data bytes. SFR[7] is self-clearing, therefore, if multiple address
bytes need to be transmitted, then SFR[7] will need to be set prior to each address byte written into the TX
FIFO. During initialization, the parity must be set to Force Parity 0 (LCR[5:3] = ’111’).
1.17
1.18
1.16.1
1.16.2
1.17.1
Normal Multidrop (9-bit) Mode - Receiver
Multidrop (9-bit) Mode - Transmitter
RS-485 Setup Time
RS-485 Turn-Around Delay
Auto Address Detection - Receiver
Upon receiving an address byte that matches the XOFF2 character, the receiver will be
40.).
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
PRELIMINARY
23
40.). The delay optimizes the time needed for the
(See ”Section , SHR[7:4]: RS-
(See ”Section , SHR[3:0]: RS-
XR16M890