xr16m890 Exar Corporation, xr16m890 Datasheet - Page 34

• Manufacturer Part Number: xr16m890
• Description: Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
enable the wake up interrupt. They are defined as follows:
FCR[0]: TX and RX FIFO Enable
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FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
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FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
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FCR[3]: Enable wake up interrupt (requires EFR bit-4 = 1)
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Please refer to
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to
both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
3.5
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Disable the wake up interrupt (default).
Logic 1 = Enable the wake up interrupt.
FIFO Control Register (FCR) - Write-Only
“Section 1.20.3, Wake-up Interrupt” on page
PRELIMINARY
34
Table 10
25.
below shows the selections. Note that the
Table 10
shows the complete selections.
REV. P1.1.1