xr16m890 Exar Corporation, xr16m890 Datasheet - Page 31
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xr16m890
Manufacturer Part Number
xr16m890
Description
Uart With 128-byte Fifo And Integrated Level Shifters
Manufacturer
Exar Corporation
Datasheet
1.XR16M890.pdf
(63 pages)
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REV. P1.1.1
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an
overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error. However,
when EMSR bit-6 changes to 1 (default is 0), LSR bit 2-4 generate an interrupt when the character is received
in the RX FIFO. Please refer to
page
•
•
IER[3]: Modem Status Interrupt Enable
•
•
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
•
•
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
•
•
IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
•
•
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
•
•
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from LOW to HIGH (if enabled by EFR bit-6).
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH (if enabled by EFR bit-7).
44.
“Section 3.14, Enhanced Mode Select Register (EMSR) - Write-only” on
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
PRELIMINARY
31
XR16M890