xr16m890 Exar Corporation, xr16m890 Datasheet - Page 49

• Manufacturer Part Number: xr16m890
• Description: Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

REV. P1.1.1
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the
auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.
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EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
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These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
enabled.
If a GPIO has been configured as an interrupt, this register selects which inputs can generate a GPIO interrupt.
This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
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If a GPIO has been configured as an output, this register selects which outputs will be in three-state mode.
This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
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If a GPIO has been configured as an interrupt, this register selects the polarity that can generate a GPIO
interrupt. This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
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This register selects where a GPIO is an input or an output.
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3.20
3.21
3.22
3.23
3.24
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
Logic 0 = GPIO interrupt for this input pin is not enabled.
Logic 1 = GPIO interrupt for this input pin is enabled.
Logic 0 = GPIO output is in active mode and can be controlled via GPIOLVL register.
Logic 1 = GPIO output is in three-state mode.
Logic 0 = GPIO interrupt is generated when this input pin is low.
Logic 1 = GPIO interrupt is generated when this input pin is high.
Logic 0 = GPIO is an output.
Logic 1 = GPIO is an input (default).
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
GPIO Interrupt Enable Register (GPIOINT) - Read/Write
GPIO Three-State Control Register (GPIO3T) - Read/Write
GPIO Polarity Control Register (GPIOINV) - Read/Write
GPIO Select Register (GPIOSEL) - Read/Write
See ”Section 1.17.1, Auto Address Detection - Receiver” on page 23.
Table
5. The xoff2 is also used as auto address detect register when the auto 9-bit mode
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
PRELIMINARY
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XR16M890