xr16m890 Exar Corporation, xr16m890 Datasheet - Page 6

• Manufacturer Part Number: xr16m890
• Description: Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Pin Description
DATA BUS INTERFACE - VLIO
(RESET#)
VLIO_EN
RESET
(IRQ#)
N
IOW#
IOR#
LLA#
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CS#
INT
AME
QFN-32
P
10
28
13
14
15
31
IN
9
8
7
6
5
4
3
2
1
#
QFN-40
PIN#
12
10
37
16
17
18
40
9
8
7
6
5
4
3
2
TQFP-48
PIN#
15
13
45
10
11
12
48
9
8
7
6
5
4
3
2
T
(OD)
I/O
YPE
O
I
I
I
I
I
I
PRELIMINARY
When 16/68# pin is at logic 1 for Intel bus interface, this output
become the active high device interrupt output. The output state is
defined by the user through the software setting of MCR[3]. INT is
set to the active mode when MCR[3] is set to a logic 1. INT is set to
the three state mode when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An
external pull-up resistor is required for proper operation.
When 16/68# pin is at logic 1 for Intel bus interface, this input
becomes RESET (active high). When 16/68# pin is at logic 0 for
Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal reg-
isters and all outputs of the UART. The UART transmitter output will
be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period (see UART Reset Conditions).
VLIO Bus Enable. When VLIO_EN pin is at logic 0, the bus interface
is selected by the 16/68# pin. When VLIO_EN pin is at logic 1, the
VLIO bus interface is enabled and the 16/68# pin has no effect.
Multiplexed Address/Data lines [7:0]. The register address is
latched on the rising edge of the LLA#. After the LLA# signal goes
high, the UART enters the data phase where the data is placed on
these lines.
Read strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
Write strobe (active low). The falling edge instigates the internal
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
Chip select (active low). The falling edge starts the access to the
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
Latch Lower Address (active low). The register address is latched
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
In the Intel/Motorola mode, this pin becomes A0.
6
D
ESCRIPTION
REV. P1.1.1