xr20m1280 Exar Corporation, xr20m1280 Datasheet - Page 26
xr20m1280
Manufacturer Part Number
xr20m1280
Description
I2c/spi Uart With 128-byte Fifo And Integrated Level Shifters
Manufacturer
Exar Corporation
Datasheet
1.XR20M1280.pdf
(63 pages)
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XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
The M1280 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 20
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
F
1.21
IGURE
20. I
Internal Loopback
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
NTERNAL
L
OOPBACK
T ra n s m it S h ift R e g is te r
R e c e iv e S h ift R e g is te r
(R H R /F IF O )
(T H R /F IF O )
PRELIMINARY
26
R T S #
C T S #
D T R #
D S R #
C D #
R I#
M C R b it-4 = 1
V C C
O P 2 #
O P 1 #
V C C
V C C
T X
R X
R T S #
C T S #
D T R #
D S R #
R I#
C D #
REV. P1.1.1