xr20m1280 Exar Corporation, xr20m1280 Datasheet - Page 7

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xr20m1280

Manufacturer Part Number
xr20m1280
Description
I2c/spi Uart With 128-byte Fifo And Integrated Level Shifters
Manufacturer
Exar Corporation
Datasheet

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REV. P1.1.1
The XR20M1280 can operate with either an I
selected via the I2C/SPI# input pin.
The I
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps. The first byte sent by an I
SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The XR20M1280 responds to each write with an
acknowledge (SDA driven LOW by XR20M1280 for one clock cycle when SCL is HIGH). If the TX FIFO is full,
the XR20M1280 will respond with a negative acknowledge (SDA driven HIGH by XR20M1280 for one clock
cycle when SCL is HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I
contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See
complete details, see the I
F
F
F
1.0 FUNCTIONAL DESCRIPTIONS
1.1
1.1.1
IGURE
IGURE
IGURE
SDA
SCL
White block: host to UART
Grey block: UART to host
S
2
C-bus interface is compliant with the Standard-mode and Fast-mode I
3. I C S
4. M
5. M
CPU Interface
ADDRESS
SLAVE
I
2
C-bus Interface
2
ASTER
ASTER
START condition
TART AND
S
W
R
White block: host to UART
Grey block: UART to host
W
EADS
S
RITES
A
2
S
F
C-bus specifications.
T
ADDRESS
ROM
TOP
O
SLAVE
REGISTER
ADDRESS
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
S
LAVE
2
C
S
C-bus master contains a start bit (SDA transition from HIGH to LOW when
ONDITIONS
LAVE
(XR20M1280)
(XR20M1280)
W
A
A
S
2
C-bus interface or an SPI interface. The CPU interface is
PRELIMINARY
REGISTER
ADDRESS
ADDRESS
SLAVE
7
R
A
A
nDATA
nDATA
2
C-bus specifications. The I
Figures 3
A
A
STOP condition
P
LAST DATA
P
XR20M1280
-
2
C-bus master
5
below. For
NA
2
C-bus
P

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