xr20m1280 Exar Corporation, xr20m1280 Datasheet - Page 33

• Manufacturer Part Number: xr20m1280
• Description: I2c/spi Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

REV. P1.1.1
ISR[0]: Interrupt Status
•
•
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
ISR[4]: Interrupt Status (requires EFR bit-4 = 1)
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff, Xon or special character(s).
ISR[5]: Interrupt Status (requires EFR bit-4 = 1)
ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.
ISR[6]: GPIO Interrupt Status
This bit reports the GPIO interrupt status. When a GPIO interrupt has been generated, this bit will be the
inverse of ISR[7]. When the GPIO interrupt is not enabled, this bit will match ISR[7] for 16550 compatibility
(See
ISR[7]: FIFO Enable Status
This bit is set to a logic 0 when the FIFOs are disabled. It is set to a logic 1 when the FIFOs are enabled (See
Table
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
FCR[0]
Table
0
0
0
1
1
1
12).
12).
FIFO Disabled
FIFO Disabled
FIFO Disabled
FIFO Enabled
FIFO Enabled
FIFO Enabled
FIFO M
ODE
T
ABLE
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
GPIO I
12: FIFO E
(GPIOINT R
NTERRUPT
Yes
Yes
Yes
Yes
No
No
NABLE
EGISTER
E
NABLED
PRELIMINARY
S
)
TATUS
33
/GPIO I
GPIO I
No GPIO Interrupt
No GPIO Interrupt
No GPIO Interrupt
No GPIO Interrupt
GPIO Interrupt
GPIO Interrupt
NTERRUPT
NTERRUPT
S
TATUS
S
TATUS
Table
ISR[7]
0
0
0
1
1
1
11).
XR20M1280
ISR[6]
0
0
1
1
1
0