xr20m1280 Exar Corporation, xr20m1280 Datasheet - Page 45

• Manufacturer Part Number: xr20m1280
• Description: I2c/spi Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

REV. P1.1.1
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0].
.
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
This register replaces SPR (during a read) and is accessible when FCTR[6] = 1. This register is also
accessible when LCR = 0xBF. It is suggested to read the FIFO Level Count Register at the Scratchpad
Register location when FCTR bit-6 = 1. See
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting
or receiving data since setting LCR = 0xBF affects the data byte format.
FCTR[0]: SLEEP/PWRDN# Function Control
•
•
FCTR[1]: Reserved
This bit is reserved and should be ’0’.
FCTR[2]: IrDa RX Inversion
•
•
3.16
3.17
3.18
Logic 0 = SLEEP pin (input) is enabled. This pin can be used to force the XR20M1280 to enter the sleep
mode immediately after the next data byte that is being transmitted on the TX pin and being received on the
RX pin has been completed.
Logic 1 = PWRDN# pin (output) is enabled. When the XR20M1280 enters the sleep mode, this pin will be
LOW. When the XR20M1280 is not in sleep mode, this pin will be HIGH.
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
DLD[7]
0
0
1
1
Trigger Level Register (TRG) - Write-Only
RX/TX FIFO Level Count Register (FC) - Read-Only
Feature Control Register (FCTR) - Read/Write
DLD[6]
0
1
1
0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
T
Table
ABLE
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses same BRG.
Transmitter and Receiver uses same BRG.
PRELIMINARY
18: BRG S
16.
45
ELECT
BRG
XR20M1280