xr20m1280 Exar Corporation, xr20m1280 Datasheet - Page 42

• Manufacturer Part Number: xr20m1280
• Description: I2c/spi Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
This register provides access to some of the advanced features of XR20M1280.
SFR[0]: Enable GPIO Registers
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SFR[1]: GPIO[15:8] or GPIO[7:0] Select
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SFR[2]: GPIO Interrupt Enable
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SFR[3]: Enable/Disable fast IR mode (Requires EFR[4] = 1)
The M1280 supports the new fast IR transmission with data rate up to 1.152 Mbps.
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SFR[4]: Enable/Disable Transmitter (Requires EFR[4] = 1)
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SFR[5]: Enable/Disable Receiver (Requires EFR[4] = 1)
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SFR[6]: Enable/Disable 9-bit mode (Requires EFR[4] = 1)
For the 9-bit mode information,
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SFR[7]: TX Address Bit (Requires EFR[4] = 1)
This bit requires that forced "0" parity is enabled (LCR[5:3]=’111’). If this bit is enabled, the 9th bit of the next
byte written to THR will be a ’1’. This bit resets after a write to THR. For the 9-bit mode information,
”Section 1.18, Multidrop (9-bit) Mode - Transmitter” on page 23.
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3.11
Logic 0 = GPIO control and status registers are not enabled.
Logic 1 = GPIOLVL register is accessible at SPR register location. GPIOINT, GPIO3T, GPIOINV, GPIOSEL
registers are accessible at XON1, XON2, XOFF1, and XOFF2 register locations.
Logic 0 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[7:0].
Logic 1 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[15:8].
Logic 0 = GPIO interrupt is disabled.
Logic 1 = GPIO interrupt is enabled. GPIOs that have been configured as inputs can generate GPIO
interrupts if the bit is enabled in the GPIOINT register. The polarity of the GPIO interrupt is selected via the
GPIOINV register.
Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps (default).
Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps. For more IR mode information, please
See ”Section 1.19, Infrared Mode” on page 24.
Logic 0 = Enable Transmitter (default).
Logic 1 = Disable Transmitter.GPIO Interrupt Enable
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
Logic 0 = Normal 8-bit mode (default).
Logic 1 = Enable 9-bit or Multidrop mode.
Logic 0 = Value of 9th bit will be ’0’ (default).
Logic 1 = Value of 9th bit will be ’1’.
Special Function Register (SFR) - Write Only
See ”Section 1.17, Normal Multidrop (9-bit) Mode - Receiver” on page 23.
PRELIMINARY
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REV. P1.1.1
See