74LCX10MTCX Fairchild Semiconductor, 74LCX10MTCX Datasheet

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74LCX10MTCX

Manufacturer Part Number
74LCX10MTCX
Description
IC GATE NAND TRPL 3IN LV 14TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX10MTCX

Logic Type
NAND Gate
Number Of Inputs
3
Number Of Circuits
3
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74LCX10M
74LCX10SJ
74LCX10MTC
74LCX10
Low Voltage Triple 3-Input NAND Gate
with 5V Tolerant Inputs
General Description
The LCX10 contains three 3-input NAND gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
The 74LCX10 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Pin Descriptions
Order Number
Pin Names
A
n
, B
O
n
n
Package Number
, C
n
MTC14
IEEE/IEC
M14D
M14A
Description
Outputs
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Inputs
DS500453
Features
Connection Diagram
Truth Table
H
L
5V tolerant inputs
2.3V–3.6V V
4.9 ns t
Power down high impedance inputs and outputs
r
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
LOW Voltage Level
HIGH Voltage Level
24 mA output drive (V
Human body model
Machine model
Package Description
PD
max (V
A
X
X
H
L
CC
n
specifications provided
CC
!
O
200V
n
B
H
X
X
!
L
3.3V), 10
CC
n
X
2000V
A
n
Immaterial
3.0V)
B
June 2000
Revised February 2005
n
C
C
X
X
H
L
P
n
n
A I
CC
www.fairchildsemi.com
max
O
H
H
H
L
n

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74LCX10MTCX Summary of contents

Page 1

... Pb-Free package per JEDEC J-STD-020B. Logic Symbol IEEE/IEC Pin Descriptions Pin Names Description Inputs Outputs n © 2005 Fairchild Semiconductor Corporation Features 5V tolerant inputs 2.3V–3.6V V specifications provided CC 4 max (V 3.3V Power down high impedance inputs and outputs output drive (V CC Implements patented noise/EMI reduction circuitry ...

Page 2

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 3

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t PLH t Output to Output Skew (Note 4) OSHL t OSLH Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any ...

Page 4

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Test t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input ...

Page 5

Schematic Diagram Generic for LCX Family 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M14A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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