wm8961 Wolfson Microelectronics plc, wm8961 Datasheet - Page 86

• Manufacturer Part Number: wm8961
• Description: Ultra-low Power Stereo Codec With 1w Stereo Class D Speaker Drivers And Ground Referenced Headphone Drivers
• Manufacturer: Wolfson Microelectronics plc

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WM8961
Register 07h Audio Interface 0
REGISTER
REGISTER
ADDRESS
Interface 0
ADDRESS
Clocking2
R7 (07h)
R8 (08h)
Audio
BIT
3:2
1:0
BIT
8:6
3:0
8
7
6
5
4
5
4
CLK_DSP_ENA
CLK_SYS_ENA
DCLKDIV[2:0]
BCLKDIV[3:0]
FORMAT[1:0]
ALRSWAP
DLRSWAP
BCLKINV
WL[1:0]
LABEL
LABEL
LRP
MS
DEFAULT
DEFAULT
0100
111
10
10
0
0
0
0
0
1
1
Swaps L and R ADC data in interface
BCLK invert bit (for master and slave modes)
0 : BCLK not inverted
1 : BCLK inverted
Master / Slave Mode Control
0 : Enable slave mode
1 : Enable master mode
Swap Left/Right channels on DAC path
Right, Left and I2S modes – LRC polarity
0 : normal LRC polarity
1 : invert LRC polarity
DSP Mode – mode A/B select
0 : MSB is available on 2
after LRC rising edge (mode A)
1 : MSB is available on 1
after LRC rising edge (mode B)
Audio Interface Word Length
00 : 16 bit
01 : 20 bit
10 : 24 bit
11 : 32 bit
Audio Interface Format
00: Right Justified
01: Left Justified
10: I2S
11: DSP
Class D switching clock divider.
000 = SYSCLK / 1
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16 (default for 12.288MHz/16 = 768 KHz)
(Note that Class D function further divides by 2 to run at 384 KHz)
Enable system clock. Power saving feature to gate clock to digital.
When this bit is enabled, an MCLK must be provided to allow access to
the control interface.
DSP clock enable. Power saving feature to gate clock to DSP while
allowing auxiliary functions to run
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = Reserved
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4 (default)
0101 = Reserved
0110 = SYSCLK / 6
0111 = SYSCLK / 8
nd
st
BCLK rising edge
BCLK rising edge
DESCRIPTION
DESCRIPTION
PP, August 2009, Rev 3.1
Pre-Production
86