wm8961 Wolfson Microelectronics plc, wm8961 Datasheet - Page 93

• Manufacturer Part Number: wm8961
• Description: Ultra-low Power Stereo Codec With 1w Stereo Class D Speaker Drivers And Ground Referenced Headphone Drivers
• Manufacturer: Wolfson Microelectronics plc

w
WM8961
Register 1Eh Clocking 3
Register 20h ADCL signal path
Register 21h ADCR signal path
Register 28h LOUT2 volume
ADCR signal
ADCL signal
REGISTER
REGISTER
REGISTER
REGISTER
Clocking 3
ADDRESS
R30 (1Eh)
ADDRESS
ADDRESS
ADDRESS
R32 (20h)
R33 (21h)
R40 (28h)
LOUT2
volume
path
path
BIT
8:7
6:1
BIT
5:4
5:4
BIT
BIT
6:0
0
8
7
CLK_256K_DIV[5:0]
LMICBOOST[1:0]
RMICBOOST[1:0]
CLK_TO_DIV[1:0]
SPKLVOL[6:0]
MANUAL_MODE
SPKLZC
SPKVU
LABEL
LABEL
LABEL
LABEL
DEFAULT
000_0000
DEFAULT
DEFAULT
DEFAULT
10_1111
0
0
00
00
00
1
Speaker PGA volume update
Left Speaker PGA zero cross enable
Left Speaker output PGA gain, 1dB steps
0000000 to 0101111 : Mute
0110000 : -73dB
…
1111001 : 0dB
…
1111111 : +6dB
Left microphone boost control
00 : 0dB
01 : 13dB
10 : 20dB
11 : 29dB
Right microphone boost control
00 : 0dB
01 : 13dB
10 : 20dB
11 : 29dB
Timeout/slow clock divider setting
00 : 125Hz
01 : 250Hz
10 : 500Hz
11 : 1kHz
256kHz clock divider setting
000000 : SYSCLK/1
000001 : SYSCLK/2
…
101111 : SYSCLK/48 (default)
…
111110 : SYSCLK/63
111111 : SYSCLK/64
Manual clock configuration Enable
0 = When low, use SAMPLE_RATE & CLK_SYS_RATE to allow
automatic configuration of system clock dividers. Excludes master
mode audio interface clocks.
1 = manual configuration of system clock dividers.
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
PP, August 2009, Rev 3.1
Pre-Production
93