sip11203 Vishay, sip11203 Datasheet - Page 12

• Manufacturer Part Number: sip11203
• Description: Sip11203 - Vishay Power Ics Synchronous Rectifier Driver With Power Up/down Control, Output Ovp, Error Amplifier And Precision Reference
• Manufacturer: Vishay

SiP11203/SiP11204
Vishay Siliconix
SYNCHRONOUS RECTIFIER PHASE-IN AND
RISING EDGE DELAY (CONT’D)
The three modes of operation experienced during syn-
chronous rectifier phase-in are, in order
The synchronous rectifier phase-in is diagrammed in
Figure 7.
Connecting R
chronous rectifier phase-in circuitry. The rectifier MOS-
FETs will then transition directly from diode-mode full
The Figure 8 below shows how the rising edge delay is
implemented in conjunction with the Si9122 and allows
the effective BBM2 and BBM4 falling delays to be
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12
• Some number of converter switching cycles may
• Some number of converter switching cycles will
• When V
occur during which ΔT
this interval, the synchronous rectifiers are held off
for a long enough time that they will act as conven
ional diodes only. This interval of operation will be
some portion of the time it takes for the voltage on
the V
occur during which 2/f
ΔT
rectifiers are held off for a portion of their possible
conduction interval, with that percentage decreas-
ing in a 1/x fashion from 100 % of their possible
conduction time to a percentage set by R
f
remainder of the time it takes for the voltage on the
V
operation occurs, with the synchronous rectifiers
being held off for a time T
time can be made equal to the inherent propagation
delay of the IC’s output drivers, as described below.
Figure 7. The SiP11203/SiP11204 gate-drive output signals are delayed during phase-in prevent disturbing the output voltage
CONVERTER
REF
DEL(FINAL)
OUT
OUT
REF
IN
IN
pin to climb to its final 1.225 V value.
A
B
A
B
REF
pin to climb to its final 1.225 V value.
DEL
Rising edge delay reduces during phase-in. Phase-in
period set R
. This interval of operation will be the
. During this interval, the synchronous
is equal to 1.225 V, normal converter
to V
L
will completely disable the syn-
DEL
CONVERTER
DEL
Phase-In period
DEL(FINAL)
≥
2/f
CONVERTER
> ΔT
. This final delay
:
DEL
DEL
. During
>
and
synchronous rectifier operation when the IC’s V
ply exceeds the UVLO
edge delay otherwise introduced by R
set to zero. (Note: By examination of the above equa-
tions, grounding the R
of setting ΔT
in practice as this will cause unnecessary power dissi-
pation in the IC: the supply current will increase by 0.15
mA if R
is shorted to ground. Also, due to the internal circuitry
of the ICs, the propagation delay time is reduced by
several nanoseconds when the R
to V
In some applications it is desirable to make use of the
rectifier phase-in feature while eliminating the residual
ΔT
should be connected from the R
the R
op-amp or comparator, such as the LMV321M7, once
the output voltage of the converter approaches its final
value. In such a circuit, V
ator should be obtained from V
SiP11204.
The phase-in of synchronous rectification helps to pre-
vent disturbances in the output voltage at start-up,
which could occur due to the differential in output volt-
age drop which occurs when the rectifier MOSFETs
make an abrupt transition from operation as diodes to
operation as synchronous rectifiers.
modified independently of rising delays BBM1 and
BBM3. For definition of the BBM delays please see the
Si9122 datasheet
DEL
L
DEL
Rising edge delay during normal operation. Period set
by R
as opposed to when it is grounded.)
. To achieve this, the appropriate resistance
DEL
DEL
pin should be pulled up to V
is connected to V
(Note: can be set to zero)
DEL
Phase-In finished
to zero. Doing so is not recommended
.
DEL
R
threshold. The residual rising-
CC
pin could be another means
for the op-amp or compar-
L
, but by 0.5 mA if this pin
S-61082–Rev. B, 19-Jun-06
DEL
Document Number: 73868
DEL
L
pin to ground, and
OUT
of the SiP11203/
IN
OUT
L
IN
pin is connected
time
B
DEL
using a suitable
A
B
A
will also be
L
sup-