sip11203 Vishay, sip11203 Datasheet - Page 9

• Manufacturer Part Number: sip11203
• Description: Sip11203 - Vishay Power Ics Synchronous Rectifier Driver With Power Up/down Control, Output Ovp, Error Amplifier And Precision Reference
• Manufacturer: Vishay

FUNCTIONAL BLOCK DIAGRAM
Figure 3. During converter startup, the synchronous MOSFET gate-driver outputs of the SiP11203/SiP11204 are reversed and inverted
START-UP DRIVER OPERATION
Assuming that V
age greater than 5.5 V, the factors controlling the rate
of rise of V
and the pre-regulator’s current limit. This gives the fol-
lowing two equations:
Document Number: 73868
S-61082–Rev. B, 19-Jun-06
• While V
• During the deadtime in which neither INB nor INA is
• The time from start-up to
• The time from start-up to
“swaps” the synchronous rectifier drive paths. This
causes the high-going signal on INB to be applied
to the gate of an n-channel hold-off MOSFET,
which is in parallel with the main OUTA driver. This
MOSFET inverts the signal from INB, which causes
its drain to be pulled towards ground. This holds
OUTA low.
driven high, the voltage on INA and that on INB will
be equal to the voltage on V
exact value of V
both OUTA and OUTB being pulled low by their
associated inverter MOSFETs.
CUVLO
UVLO
R
L
R
L
≅ (4.45 V/35 mA) x C
are the external V
≅ (4.45 V/35 mA) x C
is below the UVLO
IN
rises with suitable rapidity to a volt-
IN
, this may or may not result in
L
IN
bypass capacitor value
. Depending upon the
VL
R
VL
.
threshold, the IC
, and
to prevent spurious MOSFET switching
SW1 and SW2 are closed at start-up.
SW1 and SW2 open when V
In this way, the SiP11203/SiP11204 “swap and invert”
function prevents any unwanted turn-on of the syn-
chronous rectifiers during start-up. Once V
90 % of its final value, the drive path inside the IC is no
longer swapped, and the inverting hold-off MOSFETs
are disabled.
Once V
holding V
the V
V
These relationships are shown in Figure 4.
• During the next cycle of converter operation, all of
• The time from UVLO
REF
the above applies with the exception that INB is
now driven low, which will cause INA to be driven
high. This will in turn cause the hold-off MOSFET in
parallel with the main OUTB driver to conduct,
thereby holding OUTB low.
1.1 V ≅ (1.1 V/410 µA) x C
REF
capacitor. This gives the following equation
L
has reached 90 % of its final value, the clamp
REF
pin to rise at a rate set by the value of the
SW1
SW2
at 0 V is released, allowing the voltage on
Hold-off
MOSFET
Hold-off
MOSFET
SiP11203/SiP11204
L
> UVLO
R
to V
REF
R
VREF
.
Vishay Siliconix
attaining a voltage of
.
www.vishay.com
L
reaches
:
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