sip11203 Vishay, sip11203 Datasheet - Page 6

• Manufacturer Part Number: sip11203
• Description: Sip11203 - Vishay Power Ics Synchronous Rectifier Driver With Power Up/down Control, Output Ovp, Error Amplifier And Precision Reference
• Manufacturer: Vishay

SiP11203/SiP11204
Vishay Siliconix
DETAILED OPERATION
SUPPLY VOLTAGE (V
The SiP11203/SiP11204 are designed to operate at an
input voltage (V
chronous rectifier drivers (OUTA and OUTB) are pow-
ered directly from V
voltage for the rectifier MOSFETs. Due to the high
peak currents available from the SiP11203/SiP11204
outputs, careful attention must be paid to the bypass-
ing of V
Internal Supply (V
In order to provide the internal circuitry of the
SiP11203/SiP11204 with a stable supply voltage (V
the SiP11203/SiP11204 incorporate a linear pre-regu-
lator. Operating from V
fixed V
regulated by V
upon the voltage at the V
tion, a bypass capacitor on the order of 1µF should be
connected between V
In normal operation, V
the internal light load requirements, such as bias net-
works and the sourcing capability of the error ampli-
fier’s output.
Start-up Considerations
The average pre-regulator output current available to
charge the V
capacitor, play an important part in the start-up
sequencing of the SiP11203/SiP11204. Until V
reaches the Chip Undervoltage Lockout threshold
(CUVLO), the part is held in a low-current standby
state. When V
the majority of the on-chip circuitry is enabled, with the
exception of the reference voltage buffer and the out-
put drivers (OUTA and OUTB). Finally, when the main
Undervoltage Lockout threshold (UVLO
which occurs when V
the V
This in turn allows the V
the outputs to respond to the INA and INB inputs. See
Figure 4, in the Applications Information Section.
The I-V characteristic of the pre-regulator approximates
that of a constant current source. With V
typical I
the final regulated voltage of 5 V is 35 mA.
www.vishay.com
6
REF
L
IN
OUT
of 5 V for use by the majority of the chip. V
to PGND.
buffer and the output drivers are enabled.
at the V
L
L
REFINT
bypass capacitor, and the value of that
exceeds the CUVLO voltage of 3.55 V,
IN
) between 5.5 V and 13 V. The syn-
IN
L
L
)
, to facilitate setting the gate drive
, and therefore does not depend
L
pin for voltages between 0 V and
L
IN
L
reaches 90 % of its final value,
and GND.
IN
REF
, the pre-regulator provides a
is intended to accommodate
REF
)
pin to source current, and
pin. For proper IC opera-
R
IN
) is reached,
= 7.5 V, the
L
L
is
),
L
REFERENCE VOLTAGE (V
The SiP11203/SiP11204 incorporate an internal volt-
age reference of 2.5 V. This is scaled and buffered to
drive the V
± 1 % at 25 °C, with a temperature coefficient of
± 160 µV/°C, yielding a worst-case accuracy over tem-
perature of ± 3 % (- 40 °C to + 85 °C).
Start-up and Soft-Start Considerations
V
threshold. This allows a soft-start function to be imple-
mented by controlling the rate of rise of voltage on the
V
target voltage of the error amplifier and its associated
voltage control loop. See Figure 4, in the Applications
Information Section.
The charging rate (dV/dt) of V
choice of V
acteristic of the reference output approximates that of
a constant current source, with the typical I
V
lated voltage of 1.225 V being 410 µA. See the graph
“V
ERROR AMPLIFIER
The error amplifier is biased from the internal 5 V sup-
ply (V
to ground and up to 3.5 V. The output stage can source
in excess of 4 mA and can sink 1 mA. The output stage
is comprised of a class-A source follower working into
a 1 mA pull down (current sink), and is designed to
drive light loads such as an optocoupler and the series
resistor. The output source current I
internal 500 Ω resistor, to protect the output in the
event of a short to GND. When sourcing current in
excess of 1 mA, the voltage drop across this resistor
should be taken into account (see graph of V
I
margin, and a large signal slew rate is (1 V/µs) in a uni-
tygain configuration. The input offset voltage is typi-
cally 3 mV at 25 °C, and the offset voltage temperature
coefficient is typically 30 uV/°C. Due to its CMOS
inputs, the amplifier has low input bias and offset cur-
rents. Both amplifier inputs as well as the output are
accessible, to facilitate meeting the compensation
requirements of specific applications. Note that the
error amplifier output is clamped low until the V
age has increased past the CUVLO
LOAD
REF
REF
REF
REF
). The 1 MHz amplifier has 75 degrees of phase
L
pin for voltages between 0 V and the final regu-
is held at 0 V until V
pin, which in turn causes a gradual rise in the
Start-up.”
). The input common mode range extends down
REF
REF
pin at 1.225 V. The accuracy of V
bypass capacitor value. The I-V char-
L
REF
has exceeded its UVLO
REF
S-61082–Rev. B, 19-Jun-06
)
Document Number: 73868
is user-settable by
R
OH
voltage level.
is limited by an
OUT
OH
L
REF
at the
volt-
vs.
is
R