sip11203 Vishay, sip11203 Datasheet - Page 7

• Manufacturer Part Number: sip11203
• Description: Sip11203 - Vishay Power Ics Synchronous Rectifier Driver With Power Up/down Control, Output Ovp, Error Amplifier And Precision Reference
• Manufacturer: Vishay

MOSFET RECTIFIER DRIVERS
Start-Up
At converter start-up, V
Until such time as the UVLO
the main synchronous rectifier drivers are disabled, as
the supply voltage for the IC may be insufficient to
ensure that the output drivers will fully respond to input
commands. Without precautionary measures, capaci-
tive coupling between the drains and gates of the syn-
chronous rectifiers could cause spurious conduction in
the rectifiers. To prevent this, special hold-off MOS-
FETs are switched in until the main drivers are
enabled. These internal hold-off MOSFETs, which
connect from OUTA to PGND and OUTB to PGND,
can typically conduct in excess of 400 mA with 1 V on
OUTA or OUTB (Z
UVLO
assumes its normal mode of operation, with pulses at
INA being used to control OUTA and pulses at INB
being used to control OUTB. Figure 3 and its related
text provide additional details on this topic.
Normal Operation
When enabled, the main driver outputs are non-invert-
ing with respect to the input signal. The drivers are
designed to provide the high peak currents (2 - 4 A)
required to rapidly charge and discharge the gates of
large synchronous rectifier MOSFETs, with a greater
turn-off (pull-down) current than turn-on (pull-up) cur-
rent, to prevent shoot-through in the synchronous rec-
tifiers.
Shut-Down
In the typical application circuit, cessation of primary
timing signals at INA and INB would cause both OUTA
and OUTB to be pulled high, which at the system level
would short-circuit of the converter output to ground
via the synchronous rectifiers. To avoid possible neg-
ative effects of such an event, the SiP11203/SiP11204
uses a missing-pulses detector to monitor INA and INB
and, if necessary, set the main output drivers to a high-
impedance state. At the same time that the main driv-
ers are disabled, a pull-down device (current sink) of
user-settable value is enabled on each output, to grad-
ually discharge OUTA and OUTB, thereby performing
a soft turn-off of the rectifier MOSFETs. The pull-down
current is set by the R
Document Number: 73868
S-61082–Rev. B, 19-Jun-06
R
, the main drivers are enabled and the part
OUT
PD
L
≅ 2.5 Ω). Once V
will typically be at or near 0 V.
resistor, and is given by the
R
threshold is exceeded,
L
rises above
formula I
causes bypass capacitor at the the V
charged, preparing the IC for a voltage-loop soft-start
should the primary resume sending timing signals.
Further details are given in the Applications Informa-
tion section.
Synchronous Rectifier Phase-In
With a resistor connected between the R
ground, the SiP11203/SiP11204 will increase the low-
to-high propagation delay time from INA and INB to
OUTA and OUTB by an amount ΔT
is proportional to the resistance used, and inversely
proportional to the voltage on V
V
tions only, it constitutes a hold-off time for the synchro-
nous rectifiers. As can be seen, ΔT
V
start-up, or following any soft-start event. If ΔT
set to start at a sufficient value to allow only diode-
mode conduction in the rectifier MOSFETs, the result
will be a gentle transition from diode-mode operation to
fully synchronous rectification, thereby avoiding a sud-
den change in the average voltage drop seen at the
output rectifiers. Conventional operation can be
achieved by tying the R
rectifier phase-in function is explained in more detail in
the Applications Information section.
Output Over-voltage Protection: SiP11203 versus
SiP11204
For maximum flexibility in the way that the SiP11203/
SiP11204 parts react to an output over-voltage event,
the input to the over-voltage protect comparator
(OVP
fier inputs. Additionally, the outputs of the SiP11203
and the SiP11204 respond differently to an over-
voltage: the SiP11203 is designed to rapidly dis-
charge an output bus that is experiencing an over-volt-
age, while the SiP11204 is designed to avoid sinking
current from other supplies feeding the same bus, rely-
ing instead upon system-level intervention to provide
complete load protection. The OVP
explained in more detail in the Applications Information
section.
REF
REF
). As this delay occurs for high-going input transi-
IN
ramps from a low level to its final 1.225 V level at
) is brought out separately from the error ampli-
PULL-DOWN
= 500 V/R
SiP11203/SiP11204
DEL
pin to V
PD
REF
Vishay Siliconix
. Such an event also
L
(ΔT
. The synchronous
DEL
REF
DEL
DEL
IN
. This interval
decreases as
www.vishay.com
pin to be dis-
DEL
function is
= k x R
pin and
DEL
DEL
is
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