wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 43

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

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Pre-Production
SYSCLK CONTROL
The MCLK_SRC bit is used to select the MCLK source. The source may be either MCLK or
GPIO2/MCLK2. The selected source may also be inverted by setting register bit MCLK_INV. Note
that it is not recommended to change the control bit MCLK_INV while the WM8400 is processing
data as this may lead to clock glitches and signal pop and clicks.
The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either the
selected MCLK source or the FLL output. The selected source is divided by the SYSCLK pre-divider
MCLK_DIV to generate SYSCLK. The selected source may also be adjusted by the MCLK_DIV
divider. These register fields are described in Table 7. See “FLL” for more details of the Frequency
Locked Loop clock generator.
The WM8400 supports glitch-free MCLK and SYSCLK source selection. When both clock sources
are running and MCLK_SRC or SYSCLK_SRC is modified to select one of these clocks, a glitch-free
clock transition will take place. The de-glitching circuit will ensure that the minimum pulse width will
be no less than the pulse width of the faster of the two clock sources.
When the initial clock source is to be disabled before changing to the new clock source, the
CLK_FORCE bit must also be used to force the clock source transition to take place. In this case,
glitch-free operation cannot be guaranteed.
The SYSCLK is enabled by register bit SYSCLK_ENA.
Table 7 MCLK and SYSCLK Control
ADC / DAC SAMPLE RATES
The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the
register fields ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the SYSCLK
frequency, and according to the selected clocking mode.
R2 (02h)
R8 (08h)
REGISTER
ADDRESS
14
15
14
13
12:11
10
BIT
SYSCLK_ENA
(rw)
MCLK_SRC
SYSCLK_SRC
CLK_FORCE
MCLK_DIV
[1:0]
MCLK_INV
LABEL
DEFAULT
0b
0b
0b
0b
00b
0b
SYSCLK enable
0 = disabled
1 = enabled
MCLK Source Select
0 = MCLK pin
1 = GPIO2/MCLK2 pin
SYSCLK Source Select
0 = MCLK (or MCLK2 if MCLK_SRC=1)
1 = FLL output
Forces Clock Source Selection
0 = Existing SYSCLK source (MCLK,
MCLK2 or FLL output) must be active
when changing to a new clock source.
1 = Allows existing MCLK source to be
disabled before changing to a new clock
source.
SYSCLK Pre-divider. Clock source
(MCLK, MCLK2 or FLL output) will be
divided by this value to generate
SYSCLK.
00 = Divide SYSCLK by 1
01 = Reserved
10 = Divide SYSCLK by 2
11 = Reserved
MCLK Invert
0 = Master clock (MCLK or MCLK2) not
inverted
1 = Master clock (MCLK or MCLK2)
inverted
DESCRIPTION
PP, April 2009, Rev 3.0
WM8400
43