wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 54

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

WM8400
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ENABLING THE AUDIO CODEC
AUDIO CODEC POWER DOMAINS
Operation of the audio CODEC requires appropriate power supplies to be connected to the
associated power domains. (If the CODEC power supplies are derived from the WM8400’s integrated
LDO Regulators, then see “Power Management Subsystem” for further details of how these
Regulators are configured.)
The analogue input circuits to the CODEC are powered on the AVDD domain. The Line Outputs
LOP, LON, ROP, RON are also powered via AVDD. The digital CODEC circuits are powered on the
DCVDD domain. The supplies AVDD and DCVDD are both referenced to AGND.
The headphone outputs LOUT, ROUT, OUT3 and OUT4 are powered on the HPVDD domain
(referenced to HPGND). The speaker outputs SPKP and SPKN are power on the SPKVDD domain
(referenced to SPKGND).
The operating ranges for these supplies are detailed in the “Recommended Operating Conditions”
section.
ENABLING THE AUDIO CODEC
Before the audio CODEC can be used, it must be enabled by writing to the CODEC_ENA register bit.
When this bit is set to logic ‘0’, all CODEC registers are held in their default states. Setting this bit to
logic ‘0’ may be used to reset all CODEC registers to their default values.
The CODEC can also be enabled by writing a logic ‘1’ to the CODEC_SOFTST register bit. Setting
this bit will trigger pop-suppressed start-up sequence. As part of this sequence, CODEC_ENA will
become set automatically.
The CODEC can be disabled by writing a logic ‘1’ to the CODEC_SOFTSD register bit. Setting this
bit will trigger a pop-suppressed CODEC shut-down sequence. As part of this sequence,
CODEC_ENA will be reset to logic ‘0’.
Note that, when the WM8400 is in Deep Sleep mode (see “Power Management Subsystem”), the
CODEC will be disabled, and CODEC_ENA will be set to logic ‘0’. Therefore, on exit from Deep
Sleep mode, all the previous CODEC settings will be lost.
Table 18 Enabling the Audio CODEC
R2 (02h)
R76 (4Ch)
REGISTER
ADDRESS
15
15
14
BIT
CODEC_ENA
(rw)
CODEC_SOFT
ST
CODEC_SOFT
SD
LABEL
DEFAULT
0b
0b
0b
Master CODEC enable bit.
0 = CODEC registers held in reset
1 = CODEC registers operate normally
CODEC Soft Start Sequence
0 = Disabled
1 = Enabled
CODEC Soft Shutdown Sequence
0 = Disabled
1 = Enabled
DESCRIPTION
PP, April 2009, Rev 3.0
Pre-Production
54