bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 15

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
Table 1-2. Hardware Signal Definitions (1 of 4)
100101B
MOTEL
ALE
CS
RD/DS
WR / R/W
AD[7:0]
ADDR[7:0]
MUXED
READY
IRQ
RST
Pin Label
Motorola/Intel
Address Latch
Enable
Chip Select
Read/Data Strobe
Write/
Read/Write
Address-Data[7:0
]
Address Bus (not
multiplexed)[7:0]
Addressing Mode
Select
Ready
Interrupt Request
Reset
Signal Name
Preliminary Information/Conexant Proprietary and Confidential
I/O
I/O
OD
OD
I
I
I
I
I
I
I
I
Microcomputer Interface (MCI)
Selects between Motorola and Intel handshake conventions for the RD/DS and
WR/R/W signals.
Falling-edge-sensitive input. The value of AD[7:0] when MUXED = 1, or
ADDR[7:0] when MUXED = 0, is internally latched on the falling edge of ALE.
Active-low input used to enable read/write operations on the Microcomputer
Interface (MCI).
Bimodal input for controlling read/write access on the MCI.
DS. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data
is internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
RD. Internal data is output on AD[7:0] when RD = 0. Write operations are not
controlled by RD in this mode.
Bimodal input for controlling read/write access on the MCI.
R/W. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data
is internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
WR. External data is internally latched from AD[7:0] on the rising edge of WR.
Read operations are not controlled by WR in this mode.
8-bit bidirectional multiplexed address-data bus. AD[7] = MSB, AD[0] = LSB.
Usage is controlled using the MUXED.
Provides a glueless interface to microcomputers with separate address and data
buses. ADDR[7] = MSB, ADDR[0] = LSB. Usage is controlled using the MUXED.
Controls the MCI addressing mode.
and data (typical of Intel processors).
AD[7:0] for data only (typical of Motorola processors).
Active-low, open-drain output that indicates that the MCI is ready to transfer
data. Can be used to signal the microcomputer to insert wait states.
Active-low, open-drain output that indicates requests for interrupt. Asserted
whenever at least one unmasked interrupt flag is set. Remains inactive when-
ever no unmasked interrupt flags are present.
Asynchronous, active-low, level-sensitive input that places the transceiver in an
inactive state by setting the power-down mode bit of the Global Modes and Sta-
tus Register [global_modes; 0x00], and zeroing the clk_freq[1,0] bits of the PLL
Modes Register [pll_modes; 0x22] and the hclk_freq[1,0] bits of the Serial
Monitor Source Select Register [serial_monitor_source; 0x01]. All RAM con-
tents are lost. Does not affect the state of the test access port which is reset
automatically at power-up only.
MOTEL = 1 for Motorola protocol: DS, R/W
MOTEL = 0 for Intel protocol: RD, WR
When MOTEL = 1 and CS = 0, RD/DS behaves as an active-low data strobe
When MOTEL = 0 and CS = 0, RD/DS behaves as an active-low read strobe
When MOTEL = 1 and CS = 0, WR/R/W behaves as a read/write select line
When MOTEL = 0 and CS = 0, WR/R/W behaves as an active-low write strobe
When MUXED = 1, the MCI uses AD[7:0] as a multiplexed signal for address
When MUXED = 0, the MCI uses ADDR[7:0] as the address input, and
Conexant
Definition
1.0 System Overview
1.2 Pin Descriptions
1-7