bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 76
bt8970
Manufacturer Part Number
bt8970
Description
Single-chip Hdsl Transceiver
Manufacturer
Mindspeed Technologies
Datasheet
1.BT8970.pdf
(97 pages)
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5.0 Electrical & Mechanical Specifications
5.4 Clock Timing
Table 5-4. External Clock Timing Requirements (MCLK)
Figure 5-1. MCLK Timing Requirements
Table 5-5. HCLK Switching Characteristics
5-4
Note:(1).If an external clock is applied to XTALI/MCLK, it is referred to as MCLK.
(1)
Symbol
Symbol
The hclk_freq[1:0] control bits are located in the Serial Monitor Source Select Register [addr. 0x01].
4
5
6
7
8
1
2
3
HCLK Period (T
HCLK Period (T
(N=2)
HCLK Period (T
HCLK Pulse-Width High
HCLK Pulse-Width Low
MCLK Period (T
MCLK Pulse-Width Low
MCLK Pulse-Width High
(1)
Preliminary Information/Conexant Proprietary and Confidential
HCLK
HCLK
HCLK
MCLK
MCLK
Parameter
), hclk_freq[1:0] = ‘11’ (N=6)
), hclk_freq[1:0] = ‘00’ or ‘01’
), hclk_freq[1:0] = ‘10’ (N=4)
5.4 Clock Timing
)
(1)
Parameter
Conexant
3
(1)
(1)
1
T
T
HCLK
HCLK
Minimum
T
T
T
QCLK
QCLK
QCLK
2
Minimum
2 – 10
2 – 10
64
16
32
80
30
30
T
T
T
T
T
Typical
QCLK
QCLK
QCLK
HCLK
HCLK
Single-Chip HDSL Transceiver
64
16
32
Maximum
2
2
782
—
—
T
T
HCLK
HCLK
Maximum
T
T
T
QCLK
QCLK
QCLK
2 + 10
2 + 10
64
16
32
Units
ns
ns
ns
100101B
Bt8970
Units
100101_013
—
—
—
ns
ns
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