bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 28

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.2 Receive Section
Table 2-5. Four-Level Symbol-to-Bit Conversion
and in the four-level case it is clocked twice-per- symbol.
able to replicate the far-end input sequence, when its input is held at all ones. The locking sequence is controlled
internally, initiated through the microcomputer interface by setting the lfsr_lock bit of the detector_modes
register. The locking sequence consists of the following four steps:
2.2.6.5 Sync Detector
The sync detector compares the output of the scrambler with the output of the symbol detector. The number of
equivalent bits is accumulated for 128 comparisons. The result is then compared to a Scrambler
Synchronization Threshold Register [scr_sync_th; 0x2E], lock is declared, and the sync bit of the irq_source
register is set if the count is greater than the threshold. For a count less than or equal to the threshold, no lock
condition is declared and the sync bit is unaffected.
2.2.6.6 Detector Meters
The detector consists of five meters: a BER meter, a symbol histogrammer, a noise-level meter, a noise-level
histogram meter, and an SNR alarm meter.
scrambled ones. When the LFSR is operating as a descrambler, the meter counts the number of ones on the
descrambler output. When the LFSR is operating as a scrambler, the BER meter counts the number of equal
scrambler and symbol detector outputs. The counter operates over the meter timer interval [meter_low,
meter_high; 0x18, 0x19]. The counter is saturated to 16 bits. At the end of the measurement interval the counter
is loaded into the Bit Error Rate Meter Registers [ber_meter_low, ber_meter_high; 0x4C, 0x4D].
number of ones received during meter timer interval [meter_low, meter_high; 0x18, 0x19]. That is, at the start
of the measurement interval a counter is cleared. For each detector output which is +1 or –1, the counter is
incremented. If the detector output is +3 or –3, the count is held at its previous value. The count is saturated to
16 bits. At the end of the measurement interval, the 8 MSBs of the counter are loaded into the Symbol
Histogram Meter Register [symbol_histogram; 0x4E].
2-10
The symbol is converted to a bit stream, as shown in
The LFSR operates in the same way in both cases, except in the two-level case it is clocked once-per-symbol
When operating as a scrambler, the LFSR must first be locked to the far-end source. Once locked, it is then
1.
2.
3.
4.
The sequence continues until the lfsr_lock control bit is cleared by the microcomputer.
The BER meter provides an estimate of the bit error rate when the received symbols are known to be
The symbol histogrammer computes a coarse histogram of the received symbols. It operates by counting the
Operate the LFSR as a descrambler for 23 bits.
Operate the LFSR as a scrambler for 127 bits. The sync detector is active during this period.
Go to Step 1 if synchronization was not achieved, otherwise continue to Step 4.
Send an interrupt to the microcomputer if unmasked, indicating successful locking and continue
operating as a scrambler.
Input Symbol
–3
–1
+1
+3
Preliminary Information/Conexant Proprietary and Confidential
First Output Bit
Conexant
(sign)
0
0
1
1
Table 2-5
for the four-level case.
Second Output Bit (magnitude)
Single-Chip HDSL Transceiver
0
1
1
0
100101B
Bt8970