bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 30

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.3 Timing Recovery and Clock Interface
2.3 Timing Recovery and Clock Interface
The timing recovery and clock interface block diagram consists of the timing recovery circuit and the crystal
amplifier, as detailed in
data. Control fields include the hclk_freq[1,0] bits of the Serial Monitor Source Select Register
[serial_monitor_source; 0x01], the PLL Modes Register [pll_modes; 0x22], the Timing Recovery PLL Phase
Offset Register [pll_phase_offsset_low, pll_phase_offset_high; 0x24, 0x25] and the PLL Frequency Register
[pll_frequency_low, pll_frequency_high; 0x5E, 0x5F]. See the Register section of this datasheet for
descriptions of these control fields.
Figure 2-5. Timing Recovery and Clock Interface Block Diagram
2-12
Figure
Preliminary Information/Conexant Proprietary and Confidential
Equalizer
Detected
Symbol
Error
2-5. The main purpose of this circuitry is to recover the clock from the received
XTALI (40)
Registers
Control
Conexant
Digital Ground
Recovery
C10
Ampli er
Crystal
Timing
Circuit
Phase Detector
Meter Register
Y1
[0x40, 0x41]
XTALO (39)
C11
QCLK (87)
HCLK (35)
XOUT (36)
Single-Chip HDSL Transceiver
100101_009
100101B
Bt8970