zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 103

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7.18
I²C Address 0C1, CPU Address:h622
Accessed by CPU and I²C (R/W)
12.3.8
12.3.8.1
CPU Address 70C
Accessed by CPU (R/W) (Default 00)
12.3.8.2
CPU Address 700-705
Accessed by CPU (R/W)
12.3.8.3
CPU Address 706-70B
Accessed by CPU (R/W)
12.3.8.4
CPU Address 710
Accessed by CPU (R/W)
DEST_MAC5
[47:40]
(Default 00)
SRC_MAC5
[47:40]
(Default 00)
(Group 7 Address) Port Mirroring Group
Bits [2:0]:
Bits [7:0]
Bits [3:0]:
Bit [4]
Bit [5]
Bit [6]:
Bit [7]:
MIRROR CONTROL – Port Mirror Control Register
MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0~5
MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0~5
RMAC_MIRROR0 – RMAC Mirror 0
FCB Base Address Register 2
Source port to be mirrored
DEST_MAC4
[39:32]
(Default 00)
SRC_MAC4
[39:32]
(Default 00)
FCB Base address bit 23:16 (Default 0)
Destination port to be mirrored to.
Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0]
Mirror Flow from MIRROR_DEST_MAC[5:0] to MIRROR_SRC_MAC[5:0]
Mirror when address is destination
Mirror when address is source
DEST_MAC3
[31:24]
(Default 00)
SRC_MAC3
[31:24]
(Default 00)
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ZL50405
103
DEST_MAC2
SRC_MAC2
[23:16]
(Default 00)
[23:16]
(Default 00)
DEST_MAC1
[15:8]
(Default 00)
SRC_MAC1
[15:8]
(Default 00)
DEST_MAC0
[7:0]
(Default 00)
SRC_MAC0
[7:0]
(Default 00)
Data Sheet