zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 12

• Manufacturer Part Number: zl50405
• Description: Managed5-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

1.3
All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive.
Notes
Ball Signal Description Table
16-Bit CPU Bus Interface
A12, B12, A11, B11,
A10, B10, A9, B9, A8,
B8, A7, B7, A6, B6,
A5, B5
B4, B3, B2
A4
A3
A2
B1
Fast Ethernet Access Ports [3:0] MII
N4, P4, R4, T4, N1,
P1, R1, T1, J4, K3,
K2, K1, F4, F3, G2,
G1
T5, T2, L1, H1
Ball Signal Descriptions
Ball No(s)
P_DATA[15:0]
P_A[2:0]
P_WE#
P_RD#
P_CS#
P_INT#
M[3:0]_RXD[3:0] Input
M[3:0]_CRS_DV Input
# =
Input =
Input-ST =
Output =
I/O-TS =
pull-up =
pull-down =
Symbol
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Input & Output signal with Tri-State driver
Weak internal pull-up (nominal 100K ohm)
(refer to Section 1.4 on page 17 as some internal
pull-ups are not enabled in certain configurations)
Weak internal pull-down (nominal 100K ohm)
(refer to Section 1.4 on page 17 as some internal
pull-downs are not enabled in certain configurations)
I/O-TS
with pull-up
Input
with pull-up
Input
with pull-up
Input
Input
with pull-up
Output
with pull-up
with pull-up
Zarlink Semiconductor Inc.
ZL50405
I/O
12
Processor Bus Data Bit [15:0]. P_DATA[7:0] is
used in 8-bit mode.
Processor Bus Address Bit [2:0]
CPU Bus-Write Enable
CPU Bus-Read Enable
Chip Select
CPU Interrupt
Ports [3:0] – Receive Data Bit [3:0]
Ports [3:0] – Carrier Sense and Receive Data
Valid
Description
Data Sheet