zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 89

no-image

zl50405

Manufacturer Part Number
zl50405
Description
Managed5-port 10/100 M Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
12.3.6.7
CPU Address 515
Accessed by CPU (R/W)
12.3.6.8
I²C Address h074, CPU Address 518
Accessed by CPU and I²C (R/W)
12.3.6.9
I²C Address h075, CPU Address 519
Accessed by CPU and I²C (R/W)
Buffer reservation for class 1. Granularity 16 granules . (Default 0)
12.3.6.10
I²C Address h076, CPU Address 51A
Accessed by CPU and I²C (R/W)
Buffer reservation for class 2. Granularity 16 granules . (Default 0)
12.3.6.11
I²C Address h077, CPU Address 51B
Accessed by CPU and I²C (R/W)
Buffer reservation for class 3. Granularity 16 granules . (Default 0)
Bits [3:0]:
Bits [7:4]:
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
RDRC2 – WRED Rate Control 2
SFCB – Share FCB Size
C1RS – Class 1 Reserve Size
C3RS – Class 3 Reserve Size
C2RS – Class 2 Reserve Size
Corresponds to the frame drop percentage RB% for ingress rate control.
Granularity 6.25%.
Corresponds to the frame drop percentage RA% for ingress rate control.
Granularity 6.25%.
Expressed in multiples of 16 granules. Buffer reservation for shared pool.
Class 1 FCB Reservation
Class 2 FCB Reservation
Class 3 FCB Reservation
Zarlink Semiconductor Inc.
ZL50405
89
Data Sheet

Related parts for zl50405