am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 24

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

EAM/R
External Address Match/Reject (Input)
The incoming frame will be received dependent on the
receive operational mode of the MACE device, and the
polarity of the EAM/R pin. The EAM/R pin function is
programmed by use of the M/R bit in the Receive Frame
Control register. If the bit is set, the pin is configured as
EAM. If the bit is reset, the pin is configured as EAR.
EAM/R can be asserted during packet reception to ac-
cept or reject packets based on an external address
comparison.
Note: PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
24
SLEEP
SLEEP
AMD
0
1
1
1
1
1
0
1
1
1
1
1
PORTSEL
PORTSEL
[1–0]
[1–0]
XX
XX
XX
XX
00
01
10
11
00
01
10
11
ENPLSIO
ENPLSIO
X
X
1
1
1
1
0
1
1
1
1
0
SRDCLK Configuration
SRD Configuration
Am79C940
Interface Description
Interface Description
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
SRDCLK
Serial Receive Data Clock (Input/Output)
The Serial Receive Data (SRD) output is synchronous
to SRDCLK running at the 10MHz receive data clock fre-
quency. The pin is configured as an input, only when the
GPSI port is selected. Note that when the 10BASE-T
port is selected, transition on SRDCLK will only occur
during receive activity. When the AUI or DAI port is se-
lected, transition on SRDCLK will occur during both
transmit and receive activity.
High Impedance
SRDCLK Output
SRDCLK Output
SRDCLK Output
SRDCLK Input
High Impedance (Note 2)
High Impedance
SRD Output
SRD Output
SRD Output
SRD Output
High Impedance
Pin Function
Pin Function