am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 69

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Bit
Bit 7
Bit 6–3 RES
Bit 2
Bit 1
Bit 0
ADDRCHG
ADDRCHG Address Change. When set, al-
PHYADDR Physical Address Reset. When
LOGADDR Logical Address Reset. When
RES
Name
RES RES
RES RES
Description
lows the physical and/or logical
address to be read or pro-
grammed. When ADDRCHG is
set, ENRCV will be cleared, the
MPC will be stopped, and the last
or current in progress receive
frame will be received as normal.
After the frame completes, ac-
cess to the internal address RAM
will be permitted, indicated by the
MACE
ADDRCHG bit. Please refer to
the register description of the
ENRCV bit in the MAC Configu-
ration Control register (REG
ADDR 13) for the effect of clear-
ing the ENRCV bit. Normal re-
ception can be resumed once the
physical/logical
been
ENRCV.
Reserved. Read as zeroes.
Always write as zeroes.
set, successive reads or writes to
the Physical Address Register
will occur in the order PADR
[07–00],
PADR [47–40]. Each read or
write operation on the PADR lo-
cation will auto-increment the in-
ternal pointer to access the next
most significant byte.
set, successive reads or writes to
the Logical Address Filter will oc-
cur in the order LADRF [07–00],
LADRF
[63–56]. Each read or write op-
eration on the LADRF location
will auto-increment the internal
pointer to access the next most
significant byte.
Reserved. Read as zero. Always
write as zero.
changed,
PHYADDR
device
PADR
[15–08],....,LADRF
address
LOGADDR
clearing
by
[15–08],....,
setting
RES
has
the
Am79C940
Logical Address Filter
(LADRF [63–00])
This 64-bit mask is used to accept incoming Logical Ad-
dresses. The Logical Address Filter is expected to be
programmed at initialization (after hardware or software
reset). After a hardware or software reset and before the
ENRCV bit in the MAC Configuration Control register
has been set, the Logical Address can be accessed by
setting the LOG ADDR bit in the Internal Address Con-
figuration register (REG ADDR 18) and then by perform-
ing 8 reads or writes to the Logical Address Filter. Once
ENRCV has been set, the ADDR CHG bit in the Internal
Address Configuration register must be set and be
polled until it is cleared by the MACE device before set-
ting the LOGADDR bit and before accessing of the Logi-
cal Address Filter is allowed.
If the least significant address bit of a received message
is set (Destination Address bit 00 = 1), then the address
is deemed logical, and passed through the FCS genera-
tor. After processing the 48-bit destination address, a
32-bit resultant FCS is produced and strobed into an in-
ternal register. The high order 6-bits of this resultant
FCS are used to select one of the 64-bit positions in the
Logical Address Filter (see diagram). If the selected fil-
ter bit is a 1 , the address is accepted and the packet will
be placed in memory.
The first bit of the incoming address must be a 1 for a
logical address. If the first bit is a 0 , it is a physical ad-
dress and is compared against the value stored in the
Physical Address Register at initialization.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the user’s responsibility to
determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is always en-
abled providing that the Disable Receive Broadcast bit
(DRCVBC in the MAC Configuration Control register) is
cleared. If the Logical Address Filter is loaded with all
zeroes (and PROM = 0), all incoming logical addresses
except broadcast will be rejected.
Multicast addressing can only be performed when using
external loopback (LOOP [1–0] = 0) by programming
RCVFCSE = 1 in the User Test Register. The FCS logic
is internally allocated to the receiver section, allowing
the FCS to be computed on the incoming logical
address.
LADRF [63–00]
(REG ADDR 20)
AMD
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