am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 48

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

register and the Transmit Frame Control register can be
re-programmed if the MACE device is not transmitting.
Transmit FIFO Write
The Transmit FIFO is accessed by performing a host
generated write sequence on the MACE device. See the
Slave Access Operation-Write Access section and the
AC Waveforms section, Host System Interface, figures:
Two-Cycle Transmit FIFO/Register Write Timing and
Three-Cycle Transmit FIFO/Register Write Timing for
details of the write access timing.
There are two fundamentally different access methods
to write data into the FIFO. Using the Register Address
mode, the FIFO can be addressed using the ADD0-4
lines, (address 00001b), initiating the cycle with the CS
and R/W (low) signals. The FIFO Direct mode allows
write access to the Transmit FIFO without use of the ad-
dress lines, and using only the FDS and R/W lines. If the
MACE device detects both signals active, it will not exe-
cute a write cycle. The write cycle timing for the Register
Address or Direct FIFO modes are identical. FDS and
CS should be mutually exclusive.
The data stream to the Transmit FIFO is written using
multiple byte and/or word writes. CS or FDS does not
have to be returned inactive to commence execution of
the next write cycle. If CS/FDS is detected low at the fall-
ing edge of S0, a write cycle will commence. Note that
EOF must be asserted by the host/controller during the
last byte/word transfer.
Transmit Function Programming
The Transmit Frame Control register allows program-
ming of dynamic transmit attributes. Automatic transmit
features such as retry on collision, FCS generation/
transmission and pad field insertion can all be pro-
grammed, to provide flexibility in the (re-)transmission
of messages.
The disable retry on collision (DRTRY bit) and automatic
pad field insertion (APAD XMT bit) features should not
be changed while data remains in the Transmit FIFO.
Writing to either the DRTRY or APAD XMT bits in this
case may have unpredictable results. These bits are not
internally latched or protected. When writing to the
Transmit Frame Control register the DRTRY and APAD
XMT bits should be programmed consistently. Once the
Transmit FIFO is empty, DRTRY and APAD XMT can be
reprogrammed.
This can be achieved with no risk of transmit data loss or
corruption by clearing ENXMT after the packet data for
the current frame has been completely loaded. The
transmission will complete normally and the activation
of the INTR pin can be used to determine if the transmit
frame has completed (XMTINT will be set in the Inter-
rupt Register). Once the Transmit Frame Status has
been read, APAD XMT and/or DRTRY can be changed
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AMD
Am79C940
and ENXMT set to restart the transmit process with the
new parameters.
APAD XMT is sampled if there are less than 60 bytes in
the transmit packet when the last bit of the last byte is
transmitted. If APAD XMT is set, a pad field of pattern
00h is added until the minimum frame size of 64 bytes
(excluding preamble and SFD) is achieved. If APAD
XMT is clear, no pad field insertion will take place and
runt packet transmission is possible. When APAD XMT
is enabled, the DXMTFCS feature is over-ridden and the
four byte FCS will be added to the transmitted packet
unconditionally.
The disable FCS generation/transmission feature can
be programmed dynamically on a packet by packet ba-
sis. The current state of the DXMTFCS bit is internally
latched on the last write to the Transmit FIFO, when the
EOF indication is asserted by the host/controller.
The programming of static transmit attributes are dis-
tributed between the BIU, FIFO and MAC Configuration
Control registers.
The point at which transmission begins in relation to the
number of bytes of a frame in the FIFO is controlled by
the XMTSP bits in the BIU Configuration Control regis-
ter. Depending on the bus latency of the system,
XMTSP can be set to ensure that the Transmit FIFO
does not underflow before more data is written to the
FIFO. When the entire frame is in the FIFO, or the FIFO
becomes full before the threshold is reached, transmis-
sion of preamble will commence regardless of the value
in XMTSP. The default value of XMTSP is 64 bytes after
reset.
The point at which TDTREQ is asserted in relation to the
number of empty bytes present in the Transmit FIFO is
controlled by the XMTFW bits in the FIFO Configuration
Control register. TDTREQ will be asserted when one of
the following conditions is true:
The number of bytes free in the Transmit FIFO
relative to the current Saved Read Pointer value is
greater than or equal to the threshold set by the
XMTFW (16, 32 or 64 bytes). The Saved Read
Pointer is the first byte of the current transmit
frame, either in progress or awaiting channel
availability.
The number of bytes free in the Transmit FIFO
relative to the current Read Pointer value is
greater than or equal to the threshold set by the
XMTFW (16, 32 or 64 bytes). The Read Pointer
becomes available only after a minimum of 64 byte
frame length has been transmitted on the network
(eight bytes of preamble plus 56 bytes of data),
and points to the current byte of the frame being
transmitted.