am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 47

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

using the FIFO Direct mode, the MACE device will place
EOF in a high impedance state.
RDTREQ should be sampled on the falling edge of
SCLK. The assertion of RDTREQ is programmed by
RCVFW, and the de-assertion is modified dependent on
the state of the RCVBRST bit (both in the FIFO Configu-
ration Control register). See the section Receive FIFO
Read for additional details.
Write Access
Details of the write access timing are located in the AC
Waveforms section, Host System Interface, figures:
Two-Cycle Transmit FIFO/Register Write Timing and
Three-Cycle Transmit FIFO/Register Write Timing .
Write cycles are executed in a similar manner as the
read cycle previously described, but with the R/W input
low, and the host responsible to provide the data with
sufficient set up to the falling edge of SCLK after S2.
After a FIFO write, TDTREQ should be sampled on or
after the falling (EDSEL = HIGH) edge of SCLK after S3
of the FIFO write. The state of TDTREQ at this time will
reflect the state of the XMTFIFO.
After going active (low), TDTREQ will remain low for two
or more XMTFIFO writes.
The minimum high (inactive) time of TDTREQ is one
SCLK cycle. When EOF is written to the Transmit FIFO,
TDTREQ will go inactive after one SCLK cycle, for a
minimum of one SCLK cycle.
Initialization
After power-up, RESET should be asserted for a mini-
mum of 15 SCLK cycles to set the MACE device into a
defined state. This will set all MACE registers to their de-
fault values. The receive and transmit functions will be
turned off. A typical sequence to initialize the MACE de-
vice could look like this:
ter to change the Byte Swap mode to big endian or to
change the Transmit Start Point.
register to change the FIFO watermarks or to enable the
FIFO Burst Mode.
unwanted interrupt sources.
ister to enable the active network port. If the GPSI inter-
face is used, the register must be written twice. The first
write access should only set PORTSEL[1–0] = 11. The
second access must write again PORTSEL[1–0] = 11
and additionally set ENPLSIO = 1. This sequence is re-
quired to avoid contention on the clock, data and/or car-
rier indication signals.
Write the BIU Configuration Control (BIUCC) regis-
Write the FIFO Configuration Control (FIFOCC)
Write the Interrupt Mask Register (IMR) to disable
Write the PLS Configuration Control (PLSCC) reg-
Am79C940
ister to configure any non-default mode if the 10BASE-T
interface is used.
ter or the Physical Address Register (PADR). The Inter-
nal Address Configuration (IAC) register must be
accessed first. Set the Address Change (ADDRCHG)
bit to request access to the internal address RAM. Poll
the bit until it is cleared by the MACE device indicating
that access to the internal address RAM is permitted. In
the case of an address RAM access after hardware or
software reset (ENRCV has not been set), the MACE
device will return ADDRCHG = 0 right away. Set the
LOGADDR bit in the IAC register to select writing to the
Logical Address Filter register. Set the PHYADDR bit in
the IAC register to select writing to the Physical Address
Register. Either bit can be set together with writing the
ADDRCHG bit. Initializing the Logical Address Filter
register requires 8 write cycles. Initializing the Physical
Address Register requires 6 write cycles.
device into any of the user diagnostic modes such as
loopback.
ister as the last step in the initialization sequence to en-
able the receiver and transmitter. Note that the system
must guarantee a delay of 1 ms after power-up before
enabling the receiver and transmitter to allow the MACE
phase lock loop to stabilize.
Receive Frame Control (RCVFC) registers can be pro-
grammed on a per packet basis.
Reinitialization
The SWRST bit in the BIU Configuration Control
(BIUCC) register can be set to reset the MACE device
into a defined state for reinitialization. The same se-
quence described in the initialization section can be
used. The 1 ms delay for the MACE phase lock loop sta-
bilization need not to be observed as it only applies to a
power–up situation.
TRANSMIT OPERATION
The transmit operation and features of the MACE device
are controlled by programmable options. These options
are programmed through the BIU, FIFO and MAC Con-
figuration Control registers.
Parameters controlled by the MAC Configuration Con-
trol register are generally programmed only once,
during initialization, and are therefore static during the
normal operation of the MACE device (see the Media
Access Control section for a detailed description). The
features controlled by the FIFO Configuration Control
Write the PHY Configuration Control (PHYCC) reg-
Program the Logical Address Filter (LADRF) regis-
Write the User Test Register (UTR) to set the MACE
Write the MAC Configuration Control (MACCC) reg-
The Transmit Frame Control (XMTFC) and the
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