am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 64

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Bit 5
Bit 4–0 RES
BIU Configuration Control (BIUCC) (REG ADDR 11)
All bits within the BIU Configuration Control register will
be set to their default state upon a hardware or software
reset. Bit assignments are as follows:
Bit
Bit 7
Bit 6
Bit 5-4
64
RES
AMD
BSWP XMTSP [1–0]
XMTSP [1–0]
RDTREQ
RES
BSWP
XMTSP
[1–0]
Name
00
01
10
11
Transmit Start Point
Receive Data Transfer Request.
An internal indication of the
current request status of the Re-
ceive FIFO. RDTREQ is set
when the external RDTREQ sig-
nal is asserted.
Reserved. Read as zeroes.
Always write as zeroes.
Description
Reserved. Read as zero. Always
write as zero.
Byte Swap. The BSWP function
allows data to and from the
FIFOs to be orientated according
to little endian or big endian byte
ordering conventions. BSWP is
cleared by by activation of the
RESET pin or SWRST bit, de-
faulting to Intel byte ordering.
Transmit Start Point. XMTSP
controls the point preamble
transmission commences in rela-
tion to the number of bytes writ-
ten to the XMTFIFO. When the
entire frame is in the XMTFIFO
(or the XMTFIFO becomes full
before
achieved), transmission of pre-
amble will start regardless of the
value in XMTSP (once the IPG
time has expired). XMTSP is
given a value of 10 (64 bytes) af-
ter hardware or software reset.
Regardless of XMTSP, the FIFO
will not internally over write its
data until at least 64 bytes, or the
entire frame, has been transmit-
ted onto the network. This en-
sures that for collisions within the
slot time window, transmit data
need not be re-written to the
XMTFIFO, and re-tries will be
handled autonomously by the
MACE device.
RES
RES
the
RES
Bytes
threshold
112
16
64
4
SWRST
Am79C940
is
Bit 3-1
Bit 0
FIFO Configuration Control
(FIFOCC)
All bits within the FIFO Configuration Control register
will be set to their default state upon a hardware or soft-
ware reset. Bit assignments are as follows:
Bit
Bit 7-6
XMTFW[1–0] RCVFW [1–0] XMTFWU RCVFWU XMTBRST RCVBRST
XMTFW [1–0]
RES
SWRST
XMTFW
[1–0]
Name
00
01
10
11
Transmit FIFO Watermarks
Reserved. Read as zeroes.
Always write as zeroes.
Software Reset. When set, pro-
vides an equivalent of the hard-
ware RESET pin function. All
register bits will be set to their de-
fault values. The MACE device
will require re-initialization after
SWRST has been activated. The
MACE device will clear SWRST
during its internal reset se-
quence.
Description
Transmit
XMTFW
TDTREQ is asserted in relation
to the number of write cycles to
the Transmit FIFO. TDTREQ will
be asserted at any time that the
number of write cycles specified
by XMTFW can be executed.
XMTFW is set to a value of 00 (8
cycles) after hardware or soft-
ware reset.
The XMTFW value will only be
updated when the XMTFWU bit
is set.
To ensure that sufficient space is
present in the XMTFIFO to ac-
cept the specified number of
write cycles (including an End-
Of-Frame delimiter), TDTREQ
may go inactive before the
XMTSP threshold is reached
when using the non burst mode
(XMTBRST = 0). The host must
be aware that despite TDTREQ
going inactive, additional space
exists in the XMTFIFO, and the
data write must continue to en-
sure the XMTSP threshold is
achieved. No transmit activity will
commence until the XMTSP
controls
FIFO
Write Cycles
(REG ADDR 12)
XX
16
32
8
Watermark.
the
point