am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 55

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

from the start of reception (excluding preamble) will be
automatically deleted from the Receive FIFO with no
host intervention (the state of the RPA bit in the User
Test Register; or the RCVFW bits in the FIFO Configu-
ration Control register have no effect on this). This crite-
ria will be met, regardless of whether the receive frame
was the first (or only) frame in the Receive FIFO, or if the
receive frame was queued behind a previously received
message.
Abnormal network conditions include:
These should not occur on a correctly configured 802.3
network, but may be reported if the network has been in-
correctly configured or a fault condition exists.
Host related receive exception conditions include:
(a) Underflow caused by excessive reads from the Re-
(b) Overflow caused by lack of host reads from the Re-
(c) Missed packets due to lack of host reads from the
(a) Successive read operations from the Receive FIFO
after the final byte of data/status has been read, will
cause the DTV pin to remain de-asserted during the
read operation, indicating that no valid data is present.
There will be no adverse effect on the Receive FIFO.
(b) Data present in the Receive FIFO from packets
which completed before the overflow condition oc-
curred, can be read out by accessing the Receive FIFO
normally. Once this data (and the associated Receive
Frame Status) has been read, the EOF indication will be
asserted by the MACE device during the first read op-
eration takes place from the Receive FIFO, for the pack-
et which suffered the overflow. If there were no other
packets in the FIFO when the overflow occurred, the
EOF will be asserted on the first read from the FIFO. In
either case, the EOF indication will be accompanied by
assertion of the INTR pin, providing that the RCVINTM
bit in the Interrupt Mask Register is not set. If the Regis-
ter Address mode is being used, the host is required to
access the Receive Frame Status location using four
separate read cycles. Further access to the Receive
FIFO will be ignored by the MACE device until all four
bytes of the Receive Frame Status have been read. DTV
will not be returned if a Receive FIFO read is attempted.
If the FIFO Direct mode is being used, the host can read
FCS errors
Framing errors
Dribbling bits
Late collision
ceive FIFO (DTV will not be issued if the Receive
FIFO is empty)
ceive FIFO
Receive FIFO and/or the Receive Frame Status
Am79C940
the Receive Frame Status through the Receive FIFO,
but the host must be aware that the subsequent four cy-
cles will yield the receive status bytes, and not data from
the same or a new packet. Only the OFLO bit will be
valid in the Receive Frame Status, other error/status
and the RCVCNT fields are invalid.
While the Receive FIFO is in the overflow condition, it is
deaf to additional receive data on the network. However,
the MACE device internal address detect logic contin-
ues to operate and counts the number of packets that
would have been passed to the host under normal (non
overflow) conditions. The Missed Packet Count (MPC)
is an 8–bit count (in register 24) that maintains the num-
ber of packets which pass the address match criteria,
and complete without collision. The MPC counter will
wrap around when the maximum count of 255 is
reached, setting the MPCO (Missed Packet Count
Overflow) bit in the Interrupt Register, and asserting the
INTR pin providing that MPCOM (Missed Packet Count
Overflow Mask) in the Interrupt Mask Register is clear.
MPCO will be cleared (the interrupt will be unmasked)
after hardware or software reset. However, until the first
time that the receiver is enabled, MPC will not
increment, hence no interrupt will occur due to missed
packets after a reset.
(c) Failure to read packet data from the Receive FIFO
will eventually cause an overflow condition. The FIFO
will maintain any previously completed packet(s), which
can be read by the host at its convenience. However,
packet data on the network will no longer be received,
regardless of destination address, until the overflow is
cleared by reading the remaining Receive FIFO data
and Receive Status. The MACE device will increment
the Missed Packet Count (MPC) register to indicate that
a packet which would have been normally passed to the
host, was dropped due to the error condition.
LOOPBACK OPERATION
During loopback, the FCS logic can be allocated to the
receiver by setting RCVFCSE = 1 in User Test Register.
This permits both the transmit and receive FCS opera-
tions to be verified during the loopback process. The
state of RCVFCSE is only valid during loopback
operation.
If RCVFCSE = 0, the MACE device will calculate and ap-
pend the FCS to the transmitted message. The receive
message passed to the host will therefore contain an
additional four bytes of FCS. The Receive Frame Status
will indicate the result of the loopback operation and the
RCVCNT.
If RCVFCSE = 1, the last four bytes of the transmit mes-
sage must contain the FCS computed for the transmit
data preceding it. The MACE device will transmit the
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