s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 136

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

134
32.3.2.1 Write Timings
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V
CS# Toggling Consecutive Burst Write
Notes:
1.
2.
3.
4.
5.
LB#, UB#
CLK
ADV#
Address
CS#
WE#
Data in
WAIT#
Symbol
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
D2 is masked by UB# and LB#.
Burst Cycle Time (t
t
BEADV
t
t
t
t
CSHP
t
t
WEH
BMS
BMH
WES
BH
BS
should be met.
t
CSS(B)
WL
WH
High-Z
t
WZ
AS(B)
or t
): Data available (driven by Latency-1 clock)
t
Min
): Data don’t care (driven by CS# high going edge)
WES
BC
5
5
5
7
7
5
5
AWL
Valid
Valid
Figure 32.6 Timing Waveform of Burst Write Cycle (1)
) should not be over 2.5µs.
0
t
WL
): Data not available (driven by CS# low going edge or ADV# low going edge)
T
t
ADVS
Speed
t
ADVH
Table 32.5 Burst Write AC Characteristics
1
t
t
AH(B)
WEH
A d v a n c e
Latency 5
S71WS-Nx0 Based MCPs
2
t
Max
WH
Don’t Ca re
—
—
—
—
—
—
—
3
t
BC
t
t
BS
DS
D0
4
Units
t
DHC
ns
I n f o r m a t i o n
t
BH
D1
5
t
BMS
Symbol
D2
t
t
t
t
t
WHP
t
6
DHC
WH
WL
WZ
DS
t
D3
BMH
7
t
DHC
IH
t
, MRS# = V
WHP
t
t
CSHP
BEADV
8
t
WZ
Min
—
—
—
5
5
3
Valid
Valid
9
t
WL
Speed
S71WS-N_01_A4 September 15, 2005
10
IH
).
Latency 5
11
Max
t
10
12
WH
—
—
—
7
12
D0
13
Units
ns