s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 77

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

Notes:
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Notes:
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September 15, 2005 S71WS-N_01_A4
Addresses
Addresses
Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles.
If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
The device is in synchronous mode with wrap around.
D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 4th address in range (0-F).
Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
The device is in asynchronous mode with out wrap around.
DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 1st address in range (c-13).
AVD#
AVD#
Data
OE#
Data
CE#
RDY
OE#
CLK
CE#
RDY
CLK
Hi-Z
t
t
t
Hi-Z
AVC
t
ACS
AVC
ACS
t
CR
t
t
CR
ACH
Ac
t
ACH
Ac
1
t
1
CES
t
CES
t
AVD
t
AVD
2
A d v a n c e
2
t
7
OE
t
OE
7 cycles for initial access shown.
cycles for initial access shown.
3
3
Figure 14.9 8-word Linear Burst without Wrap Around
t
IACC
Figure 14.8 8-word Linear Burst with Wrap Around
t
IACC
4
4
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
5
5
6
6
t
RACC
t
RACC
7
t
7
RDYS
DC
t
RDYS
DC
t
BDH
t
DD
BDH
DD
t
BACC
t
BACC
DE
DE
DF
DF
D8
D8
t
RACC
DB
DB
t
RACC
75