s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 182

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

49 Transition Timing Waveform Between Read And Write
180
Latency = 5, Burst Length = 4, WP = Low enable (MRS# = V
Notes:
1.
2.
3.
4.
LB#, UB#
CLK
ADV#
Address
CS#
WE#
OE#
Data in
Data out
WAIT#
Table 49.1 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
Burst Cycle Time (t
Symbol
t
BEADV
BEADV
Figure 49.1 Synchronous Burst Read to Asynchronous Write (Address Latch Type)
should be met.
t
ADVS
t
AS(B)
WL
WH
Valid
WZ
or t
): Data available (driven by Latency-1 clock)
High-Z
0
Min
): Data don’t care (driven by CS# high going edge)
BC
t
7
AWL
T
WL
High -Z
t
) should not be over 2.5µs.
CSS(B)
t
1
ADVH
): Data not available (driven by CS# low going edge or ADV# low going edge)
t
AH(B)
Latency 5
Don’t Ca re
Speed
2
A d v a n c e
3
S71WS-Nx0 Based MCPs
t
Max
4
t
t
WH
OEL
BEL
—
t
BC
5
t
CD
DQ0
6
Units
DQ1
7
ns
t
OH
I n f o r m a t i o n
DQ2
8
DQ3
9
Symbol
t
t
t
BEADV
WZ
WLRL
t
t
AS(A)
HZ
10 11
Valid
t
AS
t
AH(A)
t
IH
12 13
ADV
t
CSS(A)
).
Min
t
1
WLRL
14 15 16 17 18
High-Z
t
t
AW
CW
Read Laten cy 5
Speed
t
S71WS-N_01_A4 September 15, 2005
BW
t
WP
High- Z
Max
—
Data Valid
t
DW
19 20
t
DH
Units
clock
21