s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 54

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

10.6
10.7
10.8 Handshaking
52
Simultaneous Read/Write
Writing Commands/Command Sequences
The simultaneous read/write feature allows the host system to read data from one bank of mem-
ory while programming or erasing another bank of memory. An erase operation may also be
suspended to read from or program another location within the same bank (except the sector
being erased).
cycles may be initiated for simultaneous operation with zero latency. Refer to the
istics (CMOS Compatible)
specification.
When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able
to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address
latches are supported in the Synchronous programming mode. During a synchronous write oper-
ation, to write a command or command sequence (which includes programming data to the
device and erasing sectors of memory), the system must drive AVD# and CE# to V
to V
when writing commands or data. During an asynchronous write operation, the system must drive
CE# and WE# to V
are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of
WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 9.1–9.2
divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and
15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A “bank address” is the
set of address bits required to uniquely select a bank. Similarly, a “sector address” is the address
bits required to uniquely select a sector. I
specification for the write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asyn-
chronous” contain timing specification tables and timing diagrams for write operations.
The handshaking feature allows the host system to detect when data is ready to be read by simply
monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the initial
word of burst data becomes available after either the falling or rising edge of the RDY pin (de-
pending on the setting for bit 10 in the Configuration Register). It is recommended that the host
system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to
ensure optimal burst mode operation (see
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.
IH
when providing an address to the device, and drive WE# and CE# to V
Figure
indicate the address space that each sector occupies. The device address space is
IL
and OE# to V
14.24,
A d v a n c e
Back-to-Back Read/Write Cycle
S71WS-Nx0 Based MCPs
table for read-while-program and read-while-erase current
IH
when providing an address, command, and data. Addresses
CC2
Table
in “DC Characteristics” represents the active current
I n f o r m a t i o n
10.9,
Configuration
Timings, shows how read and write
Register).
S71WS-N_01_A4 September 15, 2005
IL
, and OE# to V
DC Character-
IL
, and OE#
IH