s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 87

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

Notes:
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September 15, 2005 S71WS-N_01_A4
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
WE#
DQ6
DQ2
RDY(1) active with data (D8 = 1 in the Configuration Register).
RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
Figure shows the device not crossing a bank in the process of performing an erase or program.
RDY does not go low and no additional wait states are required for WS ≤ 5.
Address (hex)
Embedded
RDY(1)
RDY(2)
Erasing
Enter
AVD#
OE#,
Data
CE#
CLK
(stays high)
(stays low)
Erase
7C
C124
Suspend
Figure 14.21 Latency with Boundary Crossing when Frequency > 66 MHz
A d v a n c e
Erase
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
D124
Erase Suspend
7D
C125
Address boundary occurs every 128 words, beginning at address
Read
D125
Suspend Program
t
I n f o r m a t i o n
C126
7E
RACC
S71WS-Nx0 Based MCPs
Enter Erase
D126
Figure 14.20 DQ2 vs. DQ6
C127
7F
t
RACC
Suspend
Program
latency
Erase
D127
C127
7F
t
latency
RACC
Erase Suspend
C128
Read
80
t
RACC
D128
Resume
Erase
C129
81
Erase
D129
C130
82
D130
C131
83
Complete
Erase
85